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[/] [aemb/] [branches/] [AEMB2_712/] [rtl/] [verilog/] [aeMB_ibuf.v] - Diff between revs 61 and 63

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// $Id: aeMB_ibuf.v,v 1.5 2007-11-14 22:14:34 sybreon Exp $
// $Id: aeMB_ibuf.v,v 1.6 2007-11-14 23:39:51 sybreon Exp $
//
//
// AEMB INSTRUCTION BUFFER
// AEMB INSTRUCTION BUFFER
// 
// 
// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
//  
//  
Line 18... Line 18...
//
//
// You should have received a copy of the GNU Lesser General Public
// You should have received a copy of the GNU Lesser General Public
// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.5  2007/11/14 22:14:34  sybreon
 
// Changed interrupt handling system (reported by M. Ettus).
 
//
// Revision 1.4  2007/11/10 16:39:38  sybreon
// Revision 1.4  2007/11/10 16:39:38  sybreon
// Upgraded license to LGPLv3.
// Upgraded license to LGPLv3.
// Significant performance optimisations.
// Significant performance optimisations.
//
//
// Revision 1.3  2007/11/03 08:34:55  sybreon
// Revision 1.3  2007/11/03 08:34:55  sybreon
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   // of the pipeline so that stalls do not affect it.
   // of the pipeline so that stalls do not affect it.
 
 
   reg          rFINT;
   reg          rFINT;
   reg [1:0]     rDINT;
   reg [1:0]     rDINT;
   //wire       wSHOT = rDINT[0] & !rDINT[1] & sys_int_i;
   //wire       wSHOT = rDINT[0] & !rDINT[1] & sys_int_i;
   wire         wSHOT = !rDINT[0] & sys_int_i;
   //wire       wSHOT = !rDINT[0] & sys_int_i;
 
   wire         wSHOT = (rDINT == 2'o1);
 
 
   always @(posedge gclk)
   always @(posedge gclk)
     if (grst) begin
     if (grst) begin
        /*AUTORESET*/
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        // Beginning of autoreset for uninitialized flops
        rDINT <= 2'h0;
        rDINT <= 2'h0;
        rFINT <= 1'h0;
        rFINT <= 1'h0;
        // End of automatics
        // End of automatics
     end else if (rMSR_IE) begin
     end else if (rMSR_IE) begin
        rDINT <= #1 {rDINT[0], sys_int_i};
        rDINT <= #1 {rDINT[0], sys_int_i};
        rFINT <= (wIREG == wINTOP) ? 1'b0 : (rFINT | wSHOT);
        rFINT <= #1 (wIREG == wINTOP) ? 1'b0 : (rFINT | wSHOT);
     end
     end
 
 
   wire         fIMM = (rOPC == 6'o54);
   wire         fIMM = (rOPC == 6'o54);
   wire         fRTD = (rOPC == 6'o55);
   wire         fRTD = (rOPC == 6'o55);
   wire         fBRU = ((rOPC == 6'o46) | (rOPC == 6'o56));
   wire         fBRU = ((rOPC == 6'o46) | (rOPC == 6'o56));

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