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// $Id: aeMB_ibuf.v,v 1.6 2007-11-14 23:39:51 sybreon Exp $
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// $Id: aeMB_ibuf.v,v 1.7 2007-11-22 15:11:15 sybreon Exp $
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//
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//
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// AEMB INSTRUCTION BUFFER
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// AEMB INSTRUCTION BUFFER
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//
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//
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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//
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//
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//
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//
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// You should have received a copy of the GNU Lesser General Public
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// You should have received a copy of the GNU Lesser General Public
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// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
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// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2007/11/14 23:39:51 sybreon
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// Fixed interrupt signal synchronisation.
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//
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// Revision 1.5 2007/11/14 22:14:34 sybreon
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// Revision 1.5 2007/11/14 22:14:34 sybreon
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// Changed interrupt handling system (reported by M. Ettus).
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// Changed interrupt handling system (reported by M. Ettus).
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//
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//
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// Revision 1.4 2007/11/10 16:39:38 sybreon
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// Revision 1.4 2007/11/10 16:39:38 sybreon
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// Upgraded license to LGPLv3.
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// Upgraded license to LGPLv3.
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// TODO: Assign to FIFO not full.
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// TODO: Assign to FIFO not full.
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assign iwb_stb_o = 1'b1;
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assign iwb_stb_o = 1'b1;
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reg [31:0] rSIMM, xSIMM;
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reg [31:0] rSIMM, xSIMM;
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wire [31:0] wXCEOP = 32'hB9CE0008;
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wire [31:0] wXCEOP = 32'hBA2D0008; // Vector 0x08
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wire [31:0] wINTOP = 32'hB9CE0010;
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wire [31:0] wINTOP = 32'hB9CE0010; // Vector 0x10
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wire [31:0] wBRKOP = 32'hB9CE0018;
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wire [31:0] wBRKOP = 32'hBA0C0018; // Vector 0x18
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wire [31:0] wBRAOP = 32'h88000000;
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wire [31:0] wBRAOP = 32'h88000000; // NOP for branches
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wire [31:0] wIREG = {rOPC, rRD, rRA, rRB, rALT};
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wire [31:0] wIREG = {rOPC, rRD, rRA, rRB, rALT};
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reg [31:0] xIREG;
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reg [31:0] xIREG;
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// --- INTERRUPT LATCH --------------------------------------
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// --- INTERRUPT LATCH --------------------------------------
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// Debounce and latch onto the positive edge. This is independent
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// Debounce and latch onto the positive level. This is independent
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// of the pipeline so that stalls do not affect it.
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// of the pipeline so that stalls do not affect it.
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reg rFINT;
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reg rFINT;
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reg [1:0] rDINT;
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reg [1:0] rDINT;
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//wire wSHOT = rDINT[0] & !rDINT[1] & sys_int_i;
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wire wSHOT = rDINT[0];
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//wire wSHOT = !rDINT[0] & sys_int_i;
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wire wSHOT = (rDINT == 2'o1);
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always @(posedge gclk)
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always @(posedge gclk)
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if (grst) begin
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if (grst) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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(!fIMM & rFINT & !fRTD & !fBRU & !fBCC) ? wINTOP :
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(!fIMM & rFINT & !fRTD & !fBRU & !fBCC) ? wINTOP :
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wIDAT;
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wIDAT;
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end
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end
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always @(/*AUTOSENSE*/fIMM or rBRA or rIMM or wIDAT or xIREG) begin
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always @(/*AUTOSENSE*/fIMM or rBRA or rIMM or wIDAT or xIREG) begin
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//xSIMM <= (!fIMM | rBRA | |rXCE) ? { {(16){wIDAT[15]}}, wIDAT[15:0]} : {rIMM, wIDAT[15:0]};
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xSIMM <= (!fIMM | rBRA) ? { {(16){xIREG[15]}}, xIREG[15:0]} :
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xSIMM <= (!fIMM | rBRA) ? { {(16){xIREG[15]}}, xIREG[15:0]} :
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{rIMM, wIDAT[15:0]};
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{rIMM, wIDAT[15:0]};
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end
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end
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// --- PIPELINE --------------------------------------------
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// --- PIPELINE --------------------------------------------
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