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// $Id: aeMB_xecu.v,v 1.1 2007-11-02 03:25:41 sybreon Exp $
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// $Id: aeMB_xecu.v,v 1.2 2007-11-02 19:20:58 sybreon Exp $
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//
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//
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// AEMB MAIN EXECUTION ALU
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// AEMB MAIN EXECUTION ALU
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//
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//
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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//
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//
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// License along with this library; if not, write to the Free Software
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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// USA
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// USA
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2007/11/02 03:25:41 sybreon
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// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
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// Fixed various minor data hazard bugs.
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// Code compatible with -O0/1/2/3/s generated code.
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//
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module aeMB_xecu (/*AUTOARG*/
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module aeMB_xecu (/*AUTOARG*/
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// Outputs
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// Outputs
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dwb_adr_o, dwb_sel_o, rRESULT, rOPA, rOPB, rDWBSEL, rMSR_IE,
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dwb_adr_o, dwb_sel_o, rRESULT, rOPA, rOPB, rDWBSEL, rMSR_IE,
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rMSR_BIP,
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// Inputs
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// Inputs
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rREGA, rREGB, rMXSRC, rMXTGT, rRA, rMXALU, rBRA, rDLY, rXCE, rSIMM,
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rXCE, rREGA, rREGB, rMXSRC, rMXTGT, rRA, rMXALU, rBRA, rDLY, rSIMM,
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rIMM, rOPC, rRD, rDWBDI, rPC, rRES_MUL, rRES_BSF, gclk, grst, gena
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rIMM, rOPC, rRD, rDWBDI, rPC, rRES_MUL, rRES_BSF, gclk, grst, gena
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);
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);
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parameter DW=32;
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parameter DW=32;
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// DATA WISHBONE
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// DATA WISHBONE
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// INTERNAL
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// INTERNAL
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output [31:0] rRESULT;
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output [31:0] rRESULT;
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output [31:0] rOPA, rOPB;
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output [31:0] rOPA, rOPB;
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output [3:0] rDWBSEL;
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output [3:0] rDWBSEL;
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output rMSR_IE;
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output rMSR_IE;
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output rMSR_BIP;
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input [1:0] rXCE;
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input [31:0] rREGA, rREGB;
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input [31:0] rREGA, rREGB;
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input [1:0] rMXSRC, rMXTGT;
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input [1:0] rMXSRC, rMXTGT;
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input [4:0] rRA;
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input [4:0] rRA;
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input [2:0] rMXALU;
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input [2:0] rMXALU;
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input rBRA, rDLY;
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input rBRA, rDLY;
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input [1:0] rXCE;
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//input [1:0] rXCE;
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input [31:0] rSIMM;
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input [31:0] rSIMM;
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input [15:0] rIMM;
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input [15:0] rIMM;
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input [5:0] rOPC;
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input [5:0] rOPC;
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input [4:0] rRD;
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input [4:0] rRD;
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input [31:0] rDWBDI;
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input [31:0] rDWBDI;
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// SYSTEM
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// SYSTEM
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input gclk, grst, gena;
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input gclk, grst, gena;
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reg rMSR_C, xMSR_C;
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reg rMSR_C, xMSR_C;
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reg rMSR_IE, xMSR_IE;
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reg rMSR_IE, xMSR_IE;
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reg rMSR_BE, xMSR_BE;
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reg rMSR_BIP, xMSR_BIP;
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wire fSKIP = rBRA & !rDLY;
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// --- OPERAND SELECT
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// --- OPERAND SELECT
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reg [31:0] rOPA, rOPB;
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reg [31:0] rOPA, rOPB;
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always @(/*AUTOSENSE*/rDWBDI or rMXSRC or rPC or rREGA or rRESULT)
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always @(/*AUTOSENSE*/rDWBDI or rMXSRC or rPC or rREGA or rRESULT)
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2'o1: rOPB <= rRESULT;
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2'o1: rOPB <= rRESULT;
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2'o2: rOPB <= rDWBDI;
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2'o2: rOPB <= rDWBDI;
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2'o3: rOPB <= rSIMM;
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2'o3: rOPB <= rSIMM;
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endcase // case (rMXTGT)
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endcase // case (rMXTGT)
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// --- ADD/SUB SELECTOR ----
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// TODO: Refactor
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// TODO: Verify signed compare
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wire wADDC, wSUBC, wRES_AC, wCMPC, wOPC;
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wire [31:0] wADD, wSUB, wRES_A, wCMP, wOPX;
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wire wCMPU = (rOPA > rOPB);
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wire wCMPF = (rIMM[1]) ? wCMPU :
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((wCMPU & ~(rOPB[31] ^ rOPA[31])) | (rOPB[31] & ~rOPA[31]));
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assign {wCMPC,wCMP} = {wSUBC,wCMPF,wSUB[30:0]};
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assign wOPX = (rOPC[0] & !rOPC[5]) ? ~rOPA : rOPA ;
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assign wOPC = ((rMSR_C & rOPC[1]) | (rOPC[0] & !rOPC[1])) & (!rOPC[5] & ~&rOPC[5:4]);
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assign {wSUBC,wSUB} = {wADDC,wADD};
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assign {wADDC,wADD} = (rOPB + wOPX) + wOPC;
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reg rRES_ADDC;
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reg [31:0] rRES_ADD;
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always @(rIMM or rOPC or wADD or wADDC or wCMP
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or wCMPC or wSUB or wSUBC)
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case ({rOPC[3],rOPC[0],rIMM[0]})
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4'h2, 4'h6, 4'h7: {rRES_ADDC,rRES_ADD} <= #1 {~wSUBC,wSUB}; // SUB
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4'h3: {rRES_ADDC,rRES_ADD} <= #1 {~wCMPC,wCMP}; // CMP
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default: {rRES_ADDC,rRES_ADD} <= #1 {wADDC,wADD};
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endcase // case ({rOPC[3],rOPC[0],rIMM[0]})
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// --- LOGIC SELECTOR ---
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// --- LOGIC SELECTOR ---
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reg [31:0] rRES_LOG;
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reg [31:0] rRES_LOG;
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always @(/*AUTOSENSE*/rOPA or rOPB or rOPC)
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always @(/*AUTOSENSE*/rOPA or rOPB or rOPC)
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case (rOPC[1:0])
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case (rOPC[1:0])
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{ {(24){rOPA[7]}}, rOPA[7:0], rMSR_C};
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{ {(24){rOPA[7]}}, rOPA[7:0], rMSR_C};
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endcase // case (rIMM[6:5])
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endcase // case (rIMM[6:5])
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// --- MOVE SELECTOR ---
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// --- MOVE SELECTOR ---
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wire [31:0] wMSR = {rMSR_C, 23'h0ED32, 5'b0, rMSR_C, rMSR_IE, 1'b0};
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wire [31:0] wMSR = {rMSR_C, 3'o0,
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20'h0ED32,
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4'h0, rMSR_BIP, rMSR_C, rMSR_IE, rMSR_BE};
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wire fMFSR = (rOPC == 6'o45) & !rIMM[14] & rIMM[0];
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wire fMFSR = (rOPC == 6'o45) & !rIMM[14] & rIMM[0];
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wire fMFPC = (rOPC == 6'o45) & !rIMM[14] & !rIMM[0];
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wire fMFPC = (rOPC == 6'o45) & !rIMM[14] & !rIMM[0];
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reg [31:0] rRES_MOV;
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reg [31:0] rRES_MOV;
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always @(/*AUTOSENSE*/fMFPC or fMFSR or rOPA or rOPB or rPC or rRA
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always @(/*AUTOSENSE*/fMFPC or fMFSR or rOPA or rOPB or rPC or rRA
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or wMSR)
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or wMSR)
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rRES_MOV <= (fMFSR) ? wMSR :
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rRES_MOV <= (fMFSR) ? wMSR :
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(fMFPC) ? rPC :
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(fMFPC) ? rPC :
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(rRA[3]) ? rOPB :
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(rRA[3]) ? rOPB :
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rOPA;
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rOPA;
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// --- ADD/SUB SELECTOR ----
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// TODO: Refactor
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// TODO: Verify signed compare
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wire wADDC, wSUBC, wRES_AC, wCMPC, wOPC;
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// --- MSR REGISTER -----------------
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wire [31:0] wADD, wSUB, wRES_A, wCMP, wOPX;
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wire wCMPU = (rOPA > rOPB);
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// C
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wire wCMPF = (rIMM[1]) ? wCMPU :
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wire fMTS = (rOPC == 6'o45) & rIMM[14];
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((wCMPU & ~(rOPB[31] ^ rOPA[31])) | (rOPB[31] & ~rOPA[31]));
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wire fADDC = ({rOPC[5:4], rOPC[2]} == 3'o0);
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assign {wCMPC,wCMP} = {wSUBC,wCMPF,wSUB[30:0]};
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always @(/*AUTOSENSE*/fADDC or fMTS or fSKIP or rMSR_C or rMXALU
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assign wOPX = (rOPC[0] & !rOPC[5]) ? ~rOPA : rOPA ;
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or rOPA or rRES_ADDC or rRES_SFTC or rXCE)
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assign wOPC = ((rMSR_C & rOPC[1]) | (rOPC[0] & !rOPC[1])) & (!rOPC[5] & ~&rOPC[5:4]);
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if (fSKIP | |rXCE) begin
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xMSR_C <= rMSR_C;
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end else
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case (rMXALU)
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3'o0: xMSR_C <= (fADDC) ? rRES_ADDC : rMSR_C;
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3'o1: xMSR_C <= rMSR_C; // LOGIC
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3'o2: xMSR_C <= rRES_SFTC; // SHIFT
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3'o3: xMSR_C <= (fMTS) ? rOPA[2] : rMSR_C;
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3'o4: xMSR_C <= rMSR_C;
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3'o5: xMSR_C <= rMSR_C;
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default: xMSR_C <= 1'hX;
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endcase
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assign {wSUBC,wSUB} = {wADDC,wADD};
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// IE/BIP/BE
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assign {wADDC,wADD} = (rOPB + wOPX) + wOPC;
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wire fRTID = (rOPC == 6'o55) & rRD[0];
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wire fRTBD = (rOPC == 6'o55) & rRD[1];
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wire fBRK = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA[4:2] == 3'o3);
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reg rRES_ADDC;
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always @(/*AUTOSENSE*/fMTS or fRTID or rMSR_IE or rOPA or rXCE)
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reg [31:0] rRES_ADD;
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xMSR_IE <= (rXCE == 2'o2) ? 1'b0 :
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always @(rIMM or rOPC or wADD or wADDC or wCMP
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(fRTID) ? 1'b1 :
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or wCMPC or wSUB or wSUBC)
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(fMTS) ? rOPA[1] :
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case ({rOPC[3],rOPC[0],rIMM[0]})
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rMSR_IE;
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4'h2, 4'h6, 4'h7: {rRES_ADDC,rRES_ADD} <= #1 {~wSUBC,wSUB}; // SUB
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4'h3: {rRES_ADDC,rRES_ADD} <= #1 {~wCMPC,wCMP}; // CMP
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always @(/*AUTOSENSE*/fBRK or fMTS or fRTBD or rMSR_BIP or rOPA)
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default: {rRES_ADDC,rRES_ADD} <= #1 {wADDC,wADD};
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xMSR_BIP <= (fBRK) ? 1'b1 :
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endcase // case ({rOPC[3],rOPC[0],rIMM[0]})
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(fRTBD) ? 1'b0 :
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(fMTS) ? rOPA[3] :
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rMSR_BIP;
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always @(/*AUTOSENSE*/fMTS or rMSR_BE or rOPA)
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xMSR_BE <= (fMTS) ? rOPA[0] : rMSR_BE;
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// --- RESULT SELECTOR
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// --- RESULT SELECTOR
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wire fSKIP = rBRA & !rDLY;
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reg [31:0] rRESULT, xRESULT;
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reg [31:0] rRESULT, xRESULT;
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// RESULT
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// RESULT
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always @(/*AUTOSENSE*/fSKIP or rMXALU or rRES_ADD or rRES_BSF
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always @(/*AUTOSENSE*/fSKIP or rMXALU or rRES_ADD or rRES_BSF
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or rRES_LOG or rRES_MOV or rRES_MUL or rRES_SFT)
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or rRES_LOG or rRES_MOV or rRES_MUL or rRES_SFT)
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3'o4: xRESULT <= rRES_MUL;
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3'o4: xRESULT <= rRES_MUL;
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3'o5: xRESULT <= rRES_BSF;
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3'o5: xRESULT <= rRES_BSF;
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default: xRESULT <= 32'hX;
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default: xRESULT <= 32'hX;
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endcase // case (rMXALU)
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endcase // case (rMXALU)
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// C
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wire fMTS = (rOPC == 6'o45) & rIMM[14];
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wire fADDC = ({rOPC[5:4], rOPC[2]} == 3'o0);
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always @(/*AUTOSENSE*/fADDC or fMTS or fSKIP or rMSR_C or rMXALU
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or rOPA or rRES_ADDC or rRES_SFTC)
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if (fSKIP)
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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xMSR_C <= 1'h0;
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// End of automatics
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else
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case (rMXALU)
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3'o0: xMSR_C <= (fADDC) ? rRES_ADDC : rMSR_C;
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3'o1: xMSR_C <= rMSR_C; // LOGIC
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3'o2: xMSR_C <= rRES_SFTC; // SHIFT
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3'o3: xMSR_C <= (fMTS) ? rOPA[2] : rMSR_C;
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3'o4: xMSR_C <= rMSR_C;
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3'o5: xMSR_C <= rMSR_C;
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default: xMSR_C <= 1'hX;
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endcase
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// IE
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wire fRTID = (rOPC == 6'o55) & rRD[0];
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always @(/*AUTOSENSE*/fMTS or fRTID or rMSR_IE or rOPA) begin
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xMSR_IE <= //(rXCE == 2'o1) ? 1'b0 :
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(fRTID) ? 1'b1 :
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(fMTS) ? rOPA[1] :
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rMSR_IE;
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end
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// --- DATA WISHBONE -----
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// --- DATA WISHBONE -----
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reg [3:0] rDWBSEL, xDWBSEL;
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reg [3:0] rDWBSEL, xDWBSEL;
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assign dwb_adr_o = rRESULT[DW-1:2];
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assign dwb_adr_o = rRESULT[DW-1:2];
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assign dwb_sel_o = rDWBSEL;
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assign dwb_sel_o = rDWBSEL;
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Line 258... |
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// --- SYNC ---
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// --- SYNC ---
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always @(posedge gclk)
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always @(posedge gclk)
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if (grst) begin
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if (grst) begin
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rMSR_IE <= 1'b1;
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//rMSR_IE <= 1'b1;
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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rDWBSEL <= 4'h0;
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rDWBSEL <= 4'h0;
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rMSR_BE <= 1'h0;
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rMSR_BIP <= 1'h0;
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rMSR_C <= 1'h0;
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rMSR_C <= 1'h0;
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rMSR_IE <= 1'h0;
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rRESULT <= 32'h0;
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rRESULT <= 32'h0;
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// End of automatics
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// End of automatics
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end else if (gena) begin
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end else if (gena) begin
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rRESULT <= #1 xRESULT;
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rRESULT <= #1 xRESULT;
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rDWBSEL <= #1 xDWBSEL;
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rDWBSEL <= #1 xDWBSEL;
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rMSR_C <= #1 xMSR_C;
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rMSR_C <= #1 xMSR_C;
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rMSR_IE <= #1 xMSR_IE;
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rMSR_IE <= #1 xMSR_IE;
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rMSR_BE <= #1 xMSR_BE;
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rMSR_BIP <= #1 xMSR_BIP;
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end
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end
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// synopsys translate_off
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// synopsys translate_on
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endmodule // aeMB_xecu
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endmodule // aeMB_xecu
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