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// $Id: aeMB_xecu.v,v 1.8 2007-11-16 21:52:03 sybreon Exp $
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// $Id: aeMB_xecu.v,v 1.9 2007-11-30 16:42:51 sybreon Exp $
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//
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//
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// AEMB MAIN EXECUTION ALU
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// AEMB MAIN EXECUTION ALU
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//
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//
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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//
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//
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//
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//
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// You should have received a copy of the GNU Lesser General Public
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// You should have received a copy of the GNU Lesser General Public
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// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
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// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.8 2007/11/16 21:52:03 sybreon
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// Added fsl_tag_o to FSL bus (tag either address or data).
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//
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// Revision 1.7 2007/11/14 22:14:34 sybreon
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// Revision 1.7 2007/11/14 22:14:34 sybreon
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// Changed interrupt handling system (reported by M. Ettus).
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// Changed interrupt handling system (reported by M. Ettus).
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//
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//
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// Revision 1.6 2007/11/10 16:39:38 sybreon
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// Revision 1.6 2007/11/10 16:39:38 sybreon
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// Upgraded license to LGPLv3.
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// Upgraded license to LGPLv3.
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// INTERNAL
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// INTERNAL
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output [31:0] rRESULT;
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output [31:0] rRESULT;
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output [3:0] rDWBSEL;
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output [3:0] rDWBSEL;
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output rMSR_IE;
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output rMSR_IE;
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output rMSR_BIP;
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output rMSR_BIP;
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//input [1:0] rXCE;
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input [31:0] rREGA, rREGB;
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input [31:0] rREGA, rREGB;
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input [1:0] rMXSRC, rMXTGT;
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input [1:0] rMXSRC, rMXTGT;
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input [4:0] rRA, rRB;
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input [4:0] rRA, rRB;
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input [2:0] rMXALU;
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input [2:0] rMXALU;
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input rBRA, rDLY;
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input rBRA, rDLY;
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input [15:0] rIMM;
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input [15:0] rIMM;
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input [5:0] rOPC;
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input [5:0] rOPC;
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input [4:0] rRD;
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input [4:0] rRD;
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input [31:0] rDWBDI;
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input [31:0] rDWBDI;
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input [31:2] rPC;
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input [31:2] rPC;
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//input [31:0] rRES_MUL; // External Multiplier
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//input [31:0] rRES_BSF; // External Barrel Shifter
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// SYSTEM
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// SYSTEM
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input gclk, grst, gena;
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input gclk, grst, gena;
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reg rMSR_C, xMSR_C;
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reg rMSR_C, xMSR_C;
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(fMFPC) ? rPC :
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(fMFPC) ? rPC :
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(rRA[3]) ? rOPB :
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(rRA[3]) ? rOPB :
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rOPA;
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rOPA;
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// --- MULTIPLIER ------------------------------------------
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// --- MULTIPLIER ------------------------------------------
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// TODO: 2 stage multiplier
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reg [31:0] rRES_MUL;
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reg [31:0] rRES_MUL;
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always @(/*AUTOSENSE*/rOPA or rOPB) begin
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always @(/*AUTOSENSE*/rOPA or rOPB) begin
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rRES_MUL <= (rOPA * rOPB);
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rRES_MUL <= (rOPA * rOPB);
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end
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end
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// IE/BIP/BE
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// IE/BIP/BE
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wire fRTID = (rOPC == 6'o55) & rRD[0];
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wire fRTID = (rOPC == 6'o55) & rRD[0];
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wire fRTBD = (rOPC == 6'o55) & rRD[1];
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wire fRTBD = (rOPC == 6'o55) & rRD[1];
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wire fBRK = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA == 5'hC);
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wire fBRK = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA == 5'hC);
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wire fXCE = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA == 5'hE);
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wire fINT = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA == 5'hE);
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always @(/*AUTOSENSE*/fMTS or fRTID or fXCE or rMSR_IE or rOPA)
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always @(/*AUTOSENSE*/fINT or fMTS or fRTID or rMSR_IE or rOPA)
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xMSR_IE <= (fXCE) ? 1'b0 :
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xMSR_IE <= (fINT) ? 1'b0 :
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(fRTID) ? 1'b1 :
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(fRTID) ? 1'b1 :
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(fMTS) ? rOPA[1] :
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(fMTS) ? rOPA[1] :
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rMSR_IE;
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rMSR_IE;
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always @(/*AUTOSENSE*/fBRK or fMTS or fRTBD or rMSR_BIP or rOPA)
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always @(/*AUTOSENSE*/fBRK or fMTS or fRTBD or rMSR_BIP or rOPA)
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