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// $Id: edk32.v,v 1.2 2007-11-02 19:16:10 sybreon Exp $
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// $Id: edk32.v,v 1.3 2007-11-05 10:59:31 sybreon Exp $
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//
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//
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// AEMB EDK 3.2 Compatible Core TEST
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// AEMB EDK 3.2 Compatible Core TEST
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//
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//
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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//
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//
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// License along with this library; if not, write to the Free Software
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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// USA
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// USA
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2007/11/02 19:16:10 sybreon
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// Added interrupt simulation.
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// Changed "human readable" simulation output.
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//
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// Revision 1.1 2007/11/02 03:25:45 sybreon
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// Revision 1.1 2007/11/02 03:25:45 sybreon
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// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
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// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
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// Fixed various minor data hazard bugs.
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// Fixed various minor data hazard bugs.
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// Code compatible with -O0/1/2/3/s generated code.
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// Code compatible with -O0/1/2/3/s generated code.
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//
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//
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module edk32 ();
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module edk32 ();
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`include "random.v"
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// INITIAL SETUP //////////////////////////////////////////////////////
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// INITIAL SETUP //////////////////////////////////////////////////////
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reg sys_clk_i, sys_rst_i, sys_int_i, sys_exc_i;
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reg sys_clk_i, sys_rst_i, sys_int_i, sys_exc_i;
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reg svc;
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reg svc;
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integer inttime;
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integer inttime;
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integer seed;
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always #5 sys_clk_i = ~sys_clk_i;
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always #5 sys_clk_i = ~sys_clk_i;
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initial begin
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initial begin
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//$dumpfile("dump.vcd");
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//$dumpfile("dump.vcd");
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//$dumpvars(1,dut);
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//$dumpvars(1,dut);
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end
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end
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initial begin
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initial begin
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seed = randseed;
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svc = 0;
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svc = 0;
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sys_clk_i = 1;
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sys_clk_i = $random(seed);
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sys_rst_i = 1;
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sys_rst_i = 1;
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sys_int_i = 0;
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sys_int_i = 0;
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sys_exc_i = 0;
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sys_exc_i = 0;
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#30 sys_rst_i = 0;
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#30 sys_rst_i = 0;
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end
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end
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