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// $Id: edk32.v,v 1.4 2007-11-08 14:18:00 sybreon Exp $
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// $Id: edk32.v,v 1.5 2007-11-09 20:51:53 sybreon Exp $
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//
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//
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// AEMB EDK 3.2 Compatible Core TEST
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// AEMB EDK 3.2 Compatible Core TEST
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//
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//
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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//
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//
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// License along with this library; if not, write to the Free Software
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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// USA
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// USA
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2007/11/08 14:18:00 sybreon
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// Parameterised optional components.
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//
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// Revision 1.3 2007/11/05 10:59:31 sybreon
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// Revision 1.3 2007/11/05 10:59:31 sybreon
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// Added random seed for simulation.
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// Added random seed for simulation.
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//
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//
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// Revision 1.2 2007/11/02 19:16:10 sybreon
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// Revision 1.2 2007/11/02 19:16:10 sybreon
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// Added interrupt simulation.
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// Added interrupt simulation.
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join
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join
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// FAKE MEMORY ////////////////////////////////////////////////////////
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// FAKE MEMORY ////////////////////////////////////////////////////////
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wire [14:2] fsl_adr_o;
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wire fsl_stb_o;
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wire fsl_wre_o;
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wire [31:0] fsl_dat_o;
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wire [31:0] fsl_dat_i;
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wire [15:2] iwb_adr_o;
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wire [15:2] iwb_adr_o;
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wire iwb_stb_o;
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wire iwb_stb_o;
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wire dwb_stb_o;
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wire dwb_stb_o;
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reg [31:0] rom [0:65535];
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reg [31:0] rom [0:65535];
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wire [31:0] iwb_dat_i;
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wire [31:0] iwb_dat_i;
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reg iwb_ack_i, dwb_ack_i;
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reg iwb_ack_i, dwb_ack_i, fsl_ack_i;
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reg [31:0] ram[0:65535];
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reg [31:0] ram[0:65535];
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wire [31:0] dwb_dat_i;
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wire [31:0] dwb_dat_i;
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reg [31:0] dwblat;
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reg [31:0] dwblat;
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wire dwb_we_o;
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wire dwb_we_o;
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assign {dwb_dat_i[7:0],dwb_dat_i[15:8],dwb_dat_i[23:16],dwb_dat_i[31:24]} = ram[dadr];
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assign {dwb_dat_i[7:0],dwb_dat_i[15:8],dwb_dat_i[23:16],dwb_dat_i[31:24]} = ram[dadr];
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assign {iwb_dat_i[7:0],iwb_dat_i[15:8],iwb_dat_i[23:16],iwb_dat_i[31:24]} = ram[iadr];
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assign {iwb_dat_i[7:0],iwb_dat_i[15:8],iwb_dat_i[23:16],iwb_dat_i[31:24]} = ram[iadr];
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assign {dwb_dat_t} = ram[dwb_adr_o];
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assign {dwb_dat_t} = ram[dwb_adr_o];
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assign fsl_dat_i = fsl_adr_o;
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always @(negedge sys_clk_i) begin
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always @(negedge sys_clk_i) begin
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iwb_ack_i <= #1 iwb_stb_o;
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iwb_ack_i <= #1 iwb_stb_o;
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dwb_ack_i <= #1 dwb_stb_o;
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dwb_ack_i <= #1 dwb_stb_o;
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fsl_ack_i <= #1 fsl_stb_o;
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iadr <= #1 iwb_adr_o;
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iadr <= #1 iwb_adr_o;
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dadr <= dwb_adr_o;
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dadr <= dwb_adr_o;
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if (dwb_we_o & dwb_stb_o) begin
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if (dwb_we_o & dwb_stb_o) begin
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case (dwb_sel_o)
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case (dwb_sel_o)
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2'o0: $write("BSRLI");
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2'o0: $write("BSRLI");
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2'o1: $write("BSRAI");
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2'o1: $write("BSRAI");
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2'o2: $write("BSLLI");
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2'o2: $write("BSLLI");
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default: $write("XXX");
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default: $write("XXX");
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endcase // case (dut.rALT[10:9])
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endcase // case (dut.rALT[10:9])
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6'o33: $write("GETPUT");
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6'o33: case (dut.rRB[4:2])
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3'o0: $write("GET");
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3'o4: $write("PUT");
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3'o2: $write("NGET");
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3'o6: $write("NPUT");
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3'o1: $write("CGET");
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3'o5: $write("CPUT");
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3'o3: $write("NCGET");
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3'o7: $write("NCPUT");
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endcase // case (dut.rRB[4:2])
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6'o40: $write("OR");
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6'o40: $write("OR");
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6'o41: $write("AND");
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6'o41: $write("AND");
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6'o42: if (dut.rRD == 0) $write(" "); else $write("XOR");
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6'o42: if (dut.rRD == 0) $write(" "); else $write("XOR");
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6'o43: $write("ANDN");
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6'o43: $write("ANDN");
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// WRITEBACK
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// WRITEBACK
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$writeh("\tSR=", {dut.xecu.rMSR_BIP, dut.xecu.rMSR_C, dut.xecu.rMSR_IE, dut.xecu.rMSR_BE}," ");
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$writeh("\tSR=", {dut.xecu.rMSR_BIP, dut.xecu.rMSR_C, dut.xecu.rMSR_IE, dut.xecu.rMSR_BE}," ");
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if (dut.regf.fRDWE) begin
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if (dut.regf.fRDWE) begin
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case (dut.rMXDST)
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case (dut.rMXDST)
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2'o2: $writeh("R",dut.rRW,"=RAM(h",dut.regf.xWDAT,")");
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2'o2: begin
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if (dut.dwb_stb_o) $writeh("R",dut.rRW,"=RAM(h",dut.regf.xWDAT,")");
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if (dut.fsl_stb_o) $writeh("R",dut.rRW,"=FSL(h",dut.regf.xWDAT,")");
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end
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2'o1: $writeh("R",dut.rRW,"=LNK(h",dut.regf.xWDAT,")");
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2'o1: $writeh("R",dut.rRW,"=LNK(h",dut.regf.xWDAT,")");
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2'o0: $writeh("R",dut.rRW,"=ALU(h",dut.regf.xWDAT,")");
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2'o0: $writeh("R",dut.rRW,"=ALU(h",dut.regf.xWDAT,")");
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endcase // case (dut.rMXDST)
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endcase // case (dut.rMXDST)
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end
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end
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.dwb_adr_o(dwb_adr_o),
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.dwb_adr_o(dwb_adr_o),
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.dwb_dat_o(dwb_dat_o),
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.dwb_dat_o(dwb_dat_o),
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.dwb_dat_i(dwb_dat_i),
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.dwb_dat_i(dwb_dat_i),
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.dwb_wre_o(dwb_we_o),
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.dwb_wre_o(dwb_we_o),
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.dwb_sel_o(dwb_sel_o),
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.dwb_sel_o(dwb_sel_o),
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.fsl_ack_i(fsl_ack_i),
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.fsl_stb_o(fsl_stb_o),
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.fsl_adr_o(fsl_adr_o),
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.fsl_dat_o(fsl_dat_o),
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.fsl_dat_i(fsl_dat_i),
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.fsl_wre_o(fsl_we_o),
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.iwb_adr_o(iwb_adr_o),
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.iwb_adr_o(iwb_adr_o),
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.iwb_dat_i(iwb_dat_i),
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.iwb_dat_i(iwb_dat_i),
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.iwb_stb_o(iwb_stb_o),
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.iwb_stb_o(iwb_stb_o),
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.iwb_ack_i(iwb_ack_i),
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.iwb_ack_i(iwb_ack_i),
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.sys_clk_i(sys_clk_i),
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.sys_clk_i(sys_clk_i),
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