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// $Id: edk32.v,v 1.5 2007-11-09 20:51:53 sybreon Exp $
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// $Id: edk32.v,v 1.6 2007-11-13 23:37:28 sybreon Exp $
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//
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//
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// AEMB EDK 3.2 Compatible Core TEST
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// AEMB EDK 3.2 Compatible Core TEST
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//
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//
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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//
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//
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// License along with this library; if not, write to the Free Software
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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// USA
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// USA
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2007/11/09 20:51:53 sybreon
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// Added GET/PUT support through a FSL bus.
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//
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// Revision 1.4 2007/11/08 14:18:00 sybreon
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// Revision 1.4 2007/11/08 14:18:00 sybreon
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// Parameterised optional components.
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// Parameterised optional components.
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//
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//
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// Revision 1.3 2007/11/05 10:59:31 sybreon
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// Revision 1.3 2007/11/05 10:59:31 sybreon
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// Added random seed for simulation.
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// Added random seed for simulation.
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reg sys_clk_i, sys_rst_i, sys_int_i, sys_exc_i;
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reg sys_clk_i, sys_rst_i, sys_int_i, sys_exc_i;
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reg svc;
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reg svc;
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integer inttime;
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integer inttime;
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integer seed;
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integer seed;
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integer theend;
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always #5 sys_clk_i = ~sys_clk_i;
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always #5 sys_clk_i = ~sys_clk_i;
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initial begin
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initial begin
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$dumpfile("dump.vcd");
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//$dumpfile("dump.vcd");
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$dumpvars(1,dut);
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//$dumpvars(1,dut);
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end
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end
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initial begin
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initial begin
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seed = randseed;
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seed = randseed;
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theend = 0;
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svc = 0;
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svc = 0;
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sys_clk_i = $random(seed);
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sys_clk_i = $random(seed);
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sys_rst_i = 1;
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sys_rst_i = 1;
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sys_int_i = 0;
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sys_int_i = 0;
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sys_exc_i = 0;
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sys_exc_i = 0;
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// DISPLAY OUTPUTS ///////////////////////////////////////////////////
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// DISPLAY OUTPUTS ///////////////////////////////////////////////////
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//assign dut.rRESULT = dut.rSIMM;
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//assign dut.rRESULT = dut.rSIMM;
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integer rnd;
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integer rnd;
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always @(posedge sys_clk_i) begin
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always @(posedge sys_clk_i) begin
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// Interrupt Monitors
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// Interrupt Monitors
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if (!dut.rMSR_IE) begin
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if (!dut.rMSR_IE) begin
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rnd = $random % 30;
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rnd = $random % 30;
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// Pass/Fail Monitors
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// Pass/Fail Monitors
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if (dwb_we_o & (dwb_dat_o == "FAIL")) begin
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if (dwb_we_o & (dwb_dat_o == "FAIL")) begin
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$display("\n\tFAIL");
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$display("\n\tFAIL");
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$finish;
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$finish;
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end
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end
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if (iwb_dat_i == 32'hb8000000) begin
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if (iwb_dat_i == 32'hb8000000) begin
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theend = theend + 1;
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end
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if (theend == 5) begin
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$display("\n\t*** PASSED ALL TESTS ***");
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$display("\n\t*** PASSED ALL TESTS ***");
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$finish;
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$finish;
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end
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end
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end // always @ (posedge sys_clk_i)
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end // always @ (posedge sys_clk_i)
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