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// $Id: edk32.v,v 1.9 2007-11-20 18:36:00 sybreon Exp $
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// $Id: edk32.v,v 1.10 2007-11-30 17:08:30 sybreon Exp $
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//
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//
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// AEMB EDK 3.2 Compatible Core TEST
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// AEMB EDK 3.2 Compatible Core TEST
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//
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//
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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//
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//
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//
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//
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// You should have received a copy of the GNU Lesser General Public
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// You should have received a copy of the GNU Lesser General Public
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// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
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// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.9 2007/11/20 18:36:00 sybreon
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// Removed unnecessary byte acrobatics with VMEM data.
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//
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// Revision 1.8 2007/11/18 19:41:45 sybreon
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// Revision 1.8 2007/11/18 19:41:45 sybreon
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// Minor simulation fixes.
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// Minor simulation fixes.
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//
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//
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// Revision 1.7 2007/11/14 22:11:41 sybreon
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// Revision 1.7 2007/11/14 22:11:41 sybreon
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// Added posedge/negedge bus interface.
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// Added posedge/negedge bus interface.
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assign dwb_dat_t = ram[dwb_adr_o];
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assign dwb_dat_t = ram[dwb_adr_o];
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assign iwb_dat_i = ram[iadr];
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assign iwb_dat_i = ram[iadr];
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assign dwb_dat_i = ram[dadr];
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assign dwb_dat_i = ram[dadr];
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assign fsl_dat_i = fsl_adr_o;
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assign fsl_dat_i = fsl_adr_o;
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//`define POSEDGE
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`ifdef POSEDGE
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`ifdef POSEDGE
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always @(posedge sys_clk_i)
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always @(posedge sys_clk_i)
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if (sys_rst_i) begin
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if (sys_rst_i) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// End of automatics
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// End of automatics
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end else begin
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end else begin
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iwb_ack_i <= #1 iwb_stb_o ^ iwb_ack_i;
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iwb_ack_i <= #1 iwb_stb_o ^ iwb_ack_i;
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dwb_ack_i <= #1 dwb_stb_o ^ dwb_ack_i;
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dwb_ack_i <= #1 dwb_stb_o ^ dwb_ack_i;
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fsl_ack_i <= #1 fsl_stb_o ^ fsl_ack_i;
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fsl_ack_i <= #1 fsl_stb_o ^ fsl_ack_i;
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end
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end // else: !if(sys_rst_i)
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always @(posedge sys_clk_i) begin
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always @(posedge sys_clk_i) begin
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iadr <= #1 iwb_adr_o;
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iadr <= #1 iwb_adr_o;
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dadr <= #1 dwb_adr_o;
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dadr <= #1 dwb_adr_o;
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4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]};
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4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]};
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4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]};
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4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]};
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4'hF: ram[dwb_adr_o] <= {dwb_dat_o};
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4'hF: ram[dwb_adr_o] <= {dwb_dat_o};
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endcase // case (dwb_sel_o)
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endcase // case (dwb_sel_o)
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end // if (dwb_we_o & dwb_stb_o)
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end // if (dwb_we_o & dwb_stb_o)
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end // always @ (negedge sys_clk_i)
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end // always @ (posedge sys_clk_i)
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`else // !`ifdef POSEDGE
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`else // !`ifdef POSEDGE
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always @(negedge sys_clk_i)
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always @(negedge sys_clk_i)
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if (sys_rst_i) begin
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if (sys_rst_i) begin
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// End of automatics
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// End of automatics
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end else begin
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end else begin
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iwb_ack_i <= #1 iwb_stb_o;
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iwb_ack_i <= #1 iwb_stb_o;
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dwb_ack_i <= #1 dwb_stb_o;
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dwb_ack_i <= #1 dwb_stb_o;
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fsl_ack_i <= #1 fsl_stb_o;
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fsl_ack_i <= #1 fsl_stb_o;
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end
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end // else: !if(sys_rst_i)
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always @(negedge sys_clk_i) begin
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always @(negedge sys_clk_i) begin
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iadr <= #1 iwb_adr_o;
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iadr <= #1 iwb_adr_o;
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dadr <= #1 dwb_adr_o;
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dadr <= #1 dwb_adr_o;
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#1 $readmemh("dump.rom",ram);
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#1 $readmemh("dump.rom",ram);
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end
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end
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// DISPLAY OUTPUTS ///////////////////////////////////////////////////
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// DISPLAY OUTPUTS ///////////////////////////////////////////////////
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//assign dut.rRESULT = dut.rSIMM;
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integer rnd;
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integer rnd;
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always @(posedge sys_clk_i) begin
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always @(posedge sys_clk_i) begin
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// Interrupt Monitors
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// Interrupt Monitors
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$display("\n\t*** PASSED ALL TESTS ***");
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$display("\n\t*** PASSED ALL TESTS ***");
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$finish;
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$finish;
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end
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end
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end // always @ (posedge sys_clk_i)
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end // always @ (posedge sys_clk_i)
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always @(posedge sys_clk_i) if (dut.gena) begin
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$write ("\n", ($stime/10));
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$writeh ("\tPC=", {iwb_adr_o,2'd0});
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// DECODE
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$writeh ("\t");
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case ({dut.rBRA, dut.rDLY})
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2'b00: $write(" ");
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2'b01: $write(".");
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2'b10: $write("-");
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2'b11: $write("+");
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endcase // case ({dut.rBRA, dut.rDLY})
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case (dut.rOPC)
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6'o00: if (dut.rRD == 0) $write(" "); else $write("ADD");
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6'o01: $write("RSUB");
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6'o02: $write("ADDC");
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6'o03: $write("RSUBC");
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6'o04: $write("ADDK");
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6'o05: case (dut.rIMM[1:0])
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2'o0: $write("RSUBK");
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2'o1: $write("CMP");
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2'o3: $write("CMPU");
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default: $write("XXX");
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endcase // case (dut.rIMM[1:0])
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6'o06: $write("ADDKC");
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6'o07: $write("RSUBKC");
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6'o10: $write("ADDI");
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6'o11: $write("RSUBI");
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6'o12: $write("ADDIC");
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6'o13: $write("RSUBIC");
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6'o14: $write("ADDIK");
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6'o15: $write("RSUBIK");
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6'o16: $write("ADDIKC");
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6'o17: $write("RSUBIKC");
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6'o20: $write("MUL");
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6'o21: case (dut.rALT[10:9])
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2'o0: $write("BSRL");
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2'o1: $write("BSRA");
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2'o2: $write("BSLL");
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default: $write("XXX");
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endcase // case (dut.rALT[10:9])
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6'o22: $write("IDIV");
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6'o30: $write("MULI");
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6'o31: case (dut.rALT[10:9])
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2'o0: $write("BSRLI");
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2'o1: $write("BSRAI");
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2'o2: $write("BSLLI");
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default: $write("XXX");
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endcase // case (dut.rALT[10:9])
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6'o33: case (dut.rRB[4:2])
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3'o0: $write("GET");
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3'o4: $write("PUT");
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3'o2: $write("NGET");
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3'o6: $write("NPUT");
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3'o1: $write("CGET");
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3'o5: $write("CPUT");
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3'o3: $write("NCGET");
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3'o7: $write("NCPUT");
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endcase // case (dut.rRB[4:2])
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6'o40: $write("OR");
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6'o41: $write("AND");
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6'o42: if (dut.rRD == 0) $write(" "); else $write("XOR");
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6'o43: $write("ANDN");
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6'o44: case (dut.rIMM[6:5])
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2'o0: $write("SRA");
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2'o1: $write("SRC");
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2'o2: $write("SRL");
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2'o3: if (dut.rIMM[0]) $write("SEXT16"); else $write("SEXT8");
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endcase // case (dut.rIMM[6:5])
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6'o45: $write("MOV");
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6'o46: case (dut.rRA[3:2])
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3'o0: $write("BR");
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3'o1: $write("BRL");
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3'o2: $write("BRA");
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3'o3: $write("BRAL");
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endcase // case (dut.rRA[3:2])
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6'o47: case (dut.rRD[2:0])
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3'o0: $write("BEQ");
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3'o1: $write("BNE");
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3'o2: $write("BLT");
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3'o3: $write("BLE");
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3'o4: $write("BGT");
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3'o5: $write("BGE");
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default: $write("XXX");
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endcase // case (dut.rRD[2:0])
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6'o50: $write("ORI");
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6'o51: $write("ANDI");
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6'o52: $write("XORI");
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6'o53: $write("ANDNI");
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6'o54: $write("IMMI");
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6'o55: case (dut.rRD[1:0])
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2'o0: $write("RTSD");
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2'o1: $write("RTID");
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2'o2: $write("RTBD");
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default: $write("XXX");
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endcase
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6'o56: case (dut.rRA[3:2])
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3'o0: $write("BRI");
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3'o1: $write("BRLI");
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3'o2: $write("BRAI");
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3'o3: $write("BRALI");
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endcase // case (dut.rRA[3:2])
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6'o57: case (dut.rRD[2:0])
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3'o0: $write("BEQI");
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3'o1: $write("BNEI");
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3'o2: $write("BLTI");
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3'o3: $write("BLEI");
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3'o4: $write("BGTI");
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3'o5: $write("BGEI");
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default: $write("XXX");
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endcase // case (dut.rRD[2:0])
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6'o60: $write("LBU");
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6'o61: $write("LHU");
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6'o62: $write("LW");
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6'o64: $write("SB");
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6'o65: $write("SH");
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6'o66: $write("SW");
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6'o70: $write("LBUI");
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6'o71: $write("LHUI");
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6'o72: $write("LWI");
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6'o74: $write("SBI");
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6'o75: $write("SHI");
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6'o76: $write("SWI");
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default: $write("XXX");
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endcase // case (dut.rOPC)
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case (dut.rOPC[3])
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1'b1: $writeh("\tr",dut.rRD,", r",dut.rRA,", h",dut.rIMM);
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1'b0: $writeh("\tr",dut.rRD,", r",dut.rRA,", r",dut.rRB," ");
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endcase // case (dut.rOPC[3])
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// ALU
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$write("\t");
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//$writeh(" I=",dut.rSIMM);
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$writeh(" A=",dut.xecu.rOPA);
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$writeh(" B=",dut.xecu.rOPB);
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case (dut.rMXALU)
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3'o0: $write(" ADD");
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3'o1: $write(" LOG");
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3'o2: $write(" SFT");
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3'o3: $write(" MOV");
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3'o4: $write(" MUL");
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3'o5: $write(" BSF");
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default: $write(" XXX");
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endcase // case (dut.rMXALU)
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$writeh("=h",dut.xecu.xRESULT);
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// WRITEBACK
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$writeh("\tSR=", {dut.xecu.rMSR_BIP, dut.xecu.rMSR_C, dut.xecu.rMSR_IE, dut.xecu.rMSR_BE}," ");
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if (dut.regf.fRDWE) begin
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case (dut.rMXDST)
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2'o2: begin
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if (dut.dwb_stb_o) $writeh("R",dut.rRW,"=RAM(h",dut.regf.xWDAT,")");
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if (dut.fsl_stb_o) $writeh("R",dut.rRW,"=FSL(h",dut.regf.xWDAT,")");
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end
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2'o1: $writeh("R",dut.rRW,"=LNK(h",dut.regf.xWDAT,")");
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2'o0: $writeh("R",dut.rRW,"=ALU(h",dut.regf.xWDAT,")");
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endcase // case (dut.rMXDST)
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end
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// STORE
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if (dwb_stb_o & dwb_we_o) $writeh("RAM(",{dwb_adr_o,2'd0},")=",dwb_dat_o,":",dwb_sel_o);
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end // if (dut.gena)
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// INTERNAL WIRING ////////////////////////////////////////////////////
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// INTERNAL WIRING ////////////////////////////////////////////////////
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aeMB_edk32 #(16,16)
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aeMB_edk32 #(16,16)
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dut (
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dut (
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.sys_int_i(sys_int_i),
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.sys_int_i(sys_int_i),
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Line 454... |
Line 271... |
.iwb_ack_i(iwb_ack_i),
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.iwb_ack_i(iwb_ack_i),
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.sys_clk_i(sys_clk_i),
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.sys_clk_i(sys_clk_i),
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.sys_rst_i(sys_rst_i)
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.sys_rst_i(sys_rst_i)
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);
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);
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endmodule // edk32
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endmodule // edk32
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No newline at end of file
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No newline at end of file
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