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/* $Id: aeMB2_aslu.v,v 1.1 2007-12-11 00:43:17 sybreon Exp $
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/* $Id: aeMB2_aslu.v,v 1.2 2007-12-12 19:16:59 sybreon Exp $
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**
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**
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** AEMB2 INTEGER ARITHMETIC SHIFT LOGIC UNIT
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** AEMB2 INTEGER ARITHMETIC SHIFT LOGIC UNIT
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**
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**
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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**
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**
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| Line 21... |
Line 21... |
*/
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*/
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module aeMB2_aslu (/*AUTOARG*/
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module aeMB2_aslu (/*AUTOARG*/
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// Outputs
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// Outputs
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dwb_adr_o, dwb_sel_o, rSEL_MA, cwb_adr_o, cwb_tga_o, cwb_sel_o,
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dwb_adr_o, dwb_sel_o, rSEL_MA, cwb_adr_o, cwb_tga_o, cwb_sel_o,
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rMUL_MA, rRES_MA, rRES_EX, rMSR_IE, rMSR_BE, rMSR_BIP,
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rMUL_MA, rRES_MA, rRES_EX, rMSR_IE, rMSR_BE, rMSR_TXE, rMSR_BIP,
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// Inputs
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// Inputs
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rIMM_OF, rALU_OF, rOPC_OF, rRA_OF, rRD_OF, rPC_OF, rOPA_OF,
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rIMM_OF, rALU_OF, rOPC_OF, rOPC_IF, rRA_OF, rRD_OF, rOPA_OF,
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rOPB_OF, pha_i, clk_i, rst_i, ena_i
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rOPB_OF, pha_i, clk_i, rst_i, ena_i
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);
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);
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parameter DWB = 32;
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parameter DWB = 32;
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parameter TXE = 1;
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parameter MUL = 0;
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parameter MUL = 0;
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parameter BSF = 1;
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parameter BSF = 1;
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parameter FSL = 1;
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parameter FSL = 1;
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parameter TXE = 1;
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parameter LUT = 1;
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// DWB
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// DWB
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output [DWB-1:2] dwb_adr_o;
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output [DWB-1:2] dwb_adr_o;
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output [3:0] dwb_sel_o;
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output [3:0] dwb_sel_o;
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output [3:0] rSEL_MA;
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output [3:0] rSEL_MA;
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| Line 53... |
Line 51... |
output [31:0] rRES_MA,
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output [31:0] rRES_MA,
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rRES_EX;
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rRES_EX;
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output rMSR_IE,
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output rMSR_IE,
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rMSR_BE,
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rMSR_BE,
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rMSR_TXE,
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rMSR_BIP;
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rMSR_BIP;
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input [15:0] rIMM_OF;
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input [15:0] rIMM_OF;
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input [2:0] rALU_OF;
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input [2:0] rALU_OF;
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input [5:0] rOPC_OF;
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input [5:0] rOPC_OF,
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rOPC_IF;
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input [4:0] rRA_OF,
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input [4:0] rRA_OF,
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rRD_OF;
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rRD_OF;
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input [31:2] rPC_OF;
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input [31:0] rOPA_OF, // RA, PC
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input [31:0] rOPA_OF, // RA, PC
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rOPB_OF; // RB, IMM
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rOPB_OF; // RB, IMM
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// SYSTEM
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// SYSTEM
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input pha_i,
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input pha_i,
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| Line 80... |
Line 81... |
reg [DWB-1:2] dwb_adr_o;
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reg [DWB-1:2] dwb_adr_o;
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reg [3:0] dwb_sel_o;
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reg [3:0] dwb_sel_o;
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reg rMSR_BE;
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reg rMSR_BE;
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reg rMSR_BIP;
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reg rMSR_BIP;
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reg rMSR_IE;
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reg rMSR_IE;
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reg rMSR_TXE;
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reg [31:0] rMUL_MA;
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reg [31:0] rMUL_MA;
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reg [31:0] rRES_EX;
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reg [31:0] rRES_EX;
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reg [31:0] rRES_MA;
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reg [31:0] rRES_MA;
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reg [3:0] rSEL_MA;
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reg [3:0] rSEL_MA;
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// End of automatics
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// End of automatics
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reg rMSR_C0,
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reg rMSR_C0,
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rMSR_C1,
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rMSR_C1,
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rMSR_CL[0:TXE];
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rMSR_CL[0:1];
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wire [4:0] rRD = rRD_OF;
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wire [4:0] rRD = rRD_OF;
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wire [31:0] rOPA = rOPA_OF;
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wire [31:0] rOPA = rOPA_OF;
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wire [31:0] rOPB = rOPB_OF;
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wire [31:0] rOPB = rOPB_OF;
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wire [5:0] rOPC = rOPC_OF;
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wire [5:0] rOPC = rOPC_OF;
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wire [4:0] rRA = rRA_OF;
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wire [4:0] rRA = rRA_OF;
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wire [15:0] rIMM = rIMM_OF;
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wire [15:0] rIMM = rIMM_OF;
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wire [10:0] rALT = rIMM_OF[10:0];
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wire [10:0] rALT = rIMM_OF[10:0];
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// --- ADD/SUB SELECTOR ----
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/*
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C SELECTOR
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Preselects the C in the OF stage to speed things up. */
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// TODO: Optimise
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wire wMSR_CX, wMSR_C;
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assign wMSR_CX = (pha_i) ? rMSR_C0 :
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(TXE) ? rMSR_C1 : 1'bX;
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assign wMSR_C = (rOPC_IF == 6'o44) & wMSR_CX | // SRX
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(rOPC_IF[5:4] == 2'o0) & rOPC_IF[1] & wMSR_CX | // ADDC/RSUBC
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(rOPC_IF[5:4] == 2'o0) & (rOPC_IF[1:0] == 2'o1); // RSUB
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reg rMSR_C;
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always @(posedge clk_i)
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if (rst_i) begin
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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rMSR_C <= 1'h0;
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// End of automatics
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end else if (ena_i) begin
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rMSR_C <= #1 wMSR_C;
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end
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/*
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ADD/SUB SELECTOR
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Current implementation is a clutz. It needs to be
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re-implemented. It is also in the critical path. */
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// FIXME: Redesign
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// FIXME: Redesign
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// TODO: Refactor
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// TODO: Verify signed compare
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// TODO: Verify signed compare
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wire rMSR_CX = (!pha_i) ? rMSR_C0 : (TXE) ? rMSR_C1 : 1'bX;
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wire rMSR_C = (LUT) ? rMSR_CL[pha_i] : rMSR_CX;
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wire wADDC, wSUBC, wRES_AC, wCMPC, wOPC;
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wire wADDC, wSUBC, wRES_AC, wCMPC, wOPC;
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wire [31:0] wADD, wSUB, wRES_A, wCMP, wOPX;
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wire [31:0] wADD, wSUB, wRES_A, wCMP, wOPX;
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wire wCMPU = (rOPA > rOPB);
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wire wCMPU = (rOPA > rOPB);
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wire wCMPF = (rIMM[1]) ? wCMPU :
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wire wCMPF = (rIMM[1]) ? wCMPU :
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((wCMPU & ~(rOPB[31] ^ rOPA[31])) | (rOPB[31] & ~rOPA[31]));
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((wCMPU & ~(rOPB[31] ^ rOPA[31])) | (rOPB[31] & ~rOPA[31]));
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assign {wCMPC,wCMP} = {wSUBC,wCMPF,wSUB[30:0]};
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assign {wCMPC,wCMP} = {wSUBC,wCMPF,wSUB[30:0]};
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assign wOPX = (rOPC[0] & !rOPC[5]) ? ~rOPA : rOPA ;
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assign wOPX = (rOPC[0] & !rOPC[5]) ? ~rOPA : rOPA ;
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assign wOPC = ((rMSR_C & rOPC[1]) | (rOPC[0] & !rOPC[1])) & (!rOPC[5] & ~&rOPC[5:4]);
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//assign wOPC = ((wMSR_C & rOPC[1]) | (rOPC[0] & !rOPC[1])) & (!rOPC[5] & ~&rOPC[5:4]);
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assign wOPC = rMSR_C;
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assign {wSUBC,wSUB} = {wADDC,wADD};
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assign {wSUBC,wSUB} = {wADDC,wADD};
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assign {wADDC,wADD} = (rOPB + wOPX) + wOPC;
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assign {wADDC,wADD} = (rOPB + wOPX) + wOPC;
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reg rRES_ADDC;
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reg rRES_ADDC;
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| Line 131... |
Line 162... |
4'h2, 4'h6, 4'h7: {rRES_ADDC,rRES_ADD} <= #1 {~wSUBC,wSUB}; // SUB
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4'h2, 4'h6, 4'h7: {rRES_ADDC,rRES_ADD} <= #1 {~wSUBC,wSUB}; // SUB
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4'h3: {rRES_ADDC,rRES_ADD} <= #1 {~wCMPC,wCMP}; // CMP
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4'h3: {rRES_ADDC,rRES_ADD} <= #1 {~wCMPC,wCMP}; // CMP
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default: {rRES_ADDC,rRES_ADD} <= #1 {wADDC,wADD};
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default: {rRES_ADDC,rRES_ADD} <= #1 {wADDC,wADD};
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endcase // case ({rOPC[3],rOPC[0],rIMM[0]})
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endcase // case ({rOPC[3],rOPC[0],rIMM[0]})
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// --- LOGIC SELECTOR --------------------------------------
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/*
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LOGIC
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This can be combined with the shifter below.
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*/
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reg [31:0] rRES_LOG;
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reg [31:0] rRES_LOG;
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always @(/*AUTOSENSE*/rOPA or rOPB or rOPC)
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always @(/*AUTOSENSE*/rOPA or rOPB or rOPC)
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case (rOPC[1:0])
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case (rOPC[2:0])
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2'o0: rRES_LOG <= #1 rOPA | rOPB;
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2'o0: rRES_LOG <= #1 rOPA | rOPB;
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2'o1: rRES_LOG <= #1 rOPA & rOPB;
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2'o1: rRES_LOG <= #1 rOPA & rOPB;
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2'o2: rRES_LOG <= #1 rOPA ^ rOPB;
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2'o2: rRES_LOG <= #1 rOPA ^ rOPB;
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2'o3: rRES_LOG <= #1 rOPA & ~rOPB;
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2'o3: rRES_LOG <= #1 rOPA & ~rOPB;
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endcase // case (rOPC[1:0])
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endcase // case (rOPC[2:0])
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/*
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SIMPLE SHIFTER
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// --- SHIFTER SELECTOR ------------------------------------
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Implemented as wiring and registers.
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*/
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reg [31:0] rRES_SFT;
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reg [31:0] rRES_SFT;
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reg rRES_SFTC;
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reg rRES_SFTC;
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always @(/*AUTOSENSE*/rIMM or rMSR_C or rOPA)
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always @(/*AUTOSENSE*/rIMM or rMSR_C or rOPA)
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case (rIMM[6:5])
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case (rIMM[6:5])
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2'o0: {rRES_SFT, rRES_SFTC} <= #1 {rOPA[31],rOPA[31:0]};
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2'o0: rRES_SFT <= {rOPA[31],rOPA[31:1]}; // SRA
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2'o1: {rRES_SFT, rRES_SFTC} <= #1 {rMSR_C,rOPA[31:0]};
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2'o1: rRES_SFT <= {rMSR_C,rOPA[31:1]}; // SRC
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2'o2: {rRES_SFT, rRES_SFTC} <= #1 {1'b0,rOPA[31:0]};
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2'o2: rRES_SFT <= {1'b0,rOPA[31:1]}; // SRL
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2'o3: {rRES_SFT, rRES_SFTC} <= #1 (rIMM[0]) ? { {(16){rOPA[15]}}, rOPA[15:0], rMSR_C} :
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2'o3: rRES_SFT <= (rIMM[0]) ?
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{ {(24){rOPA[7]}}, rOPA[7:0], rMSR_C};
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{{(16){rOPA[15]}}, rOPA[15:0]} : // SEXT16
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{{(24){rOPA[7]}}, rOPA[7:0]}; // SEXT8
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endcase // case (rIMM[6:5])
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endcase // case (rIMM[6:5])
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// --- MOVE SELECTOR ---------------------------------------
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always @(/*AUTOSENSE*/rIMM or rMSR_C or rOPA)
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rRES_SFTC <= (&rIMM[6:5]) ? rMSR_C : rOPA[0];
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/*
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MOVE FROM SPECIAL
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MSR bits
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31 - CC (carry copy)
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30 - PHA (current phase)
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29 - TXE (enable second thread)
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3 - BIP (break in progress)
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2 - C (carry flag)
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1 - IE (interrupt enable)
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0 - BE (bus-lock enable)
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*/
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wire wTXE = (TXE) ? 2'd1 : 2'd0;
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wire wTXE = (TXE) ? 1'b1 : 1'b0;
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wire [31:0] wMSR = {rMSR_C, // MSR_CC
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wire [31:0] wMSR = {rMSR_C, // MSR_CC
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pha_i, // Current phase
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pha_i, // Current phase
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!pha_i, // Current phase
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rMSR_TXE, // Thread Execution Enabled
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wTXE, // Thread Execution Enabled
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wTXE,
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4'h0, // Reserved
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4'h0, // Reserved
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8'hAE, // Vendor
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8'hAE, // Vendor
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8'h32, // Version
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8'h32, // Version
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4'h0, // Reserved
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4'h0, // Reserved
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rMSR_BIP, // MSR_BIP
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rMSR_BIP, // MSR_BIP
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| Line 176... |
Line 230... |
rMSR_BE}; // MSR_BE
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rMSR_BE}; // MSR_BE
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wire fMFSR = (rOPC == 6'o45) & !rIMM[14] & rIMM[0];
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wire fMFSR = (rOPC == 6'o45) & !rIMM[14] & rIMM[0];
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wire fMFPC = (rOPC == 6'o45) & !rIMM[14] & !rIMM[0];
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wire fMFPC = (rOPC == 6'o45) & !rIMM[14] & !rIMM[0];
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reg [31:0] rRES_MOV;
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reg [31:0] rRES_MOV;
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always @(/*AUTOSENSE*/fMFPC or fMFSR or rOPA or rOPB or rPC_OF
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always @(/*AUTOSENSE*/fMFSR or rOPA or rOPB or rRA or wMSR)
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or rRA or wMSR)
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rRES_MOV <= (fMFSR) ? wMSR :
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rRES_MOV <= (fMFSR) ? wMSR :
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(fMFPC) ? {rPC_OF, 2'd0} :
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//(fMFPC) ? rOPA :
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(rRA[3]) ? rOPB :
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(rRA[3]) ? rOPB :
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rOPA;
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rOPA;
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// --- MULTIPLIER ------------------------------------------
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/*
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// 2-stage
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MULTIPLIER
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|
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Implemented as a 2-stage multiplier in order to increase clock
|
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speed. */
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reg [31:0] rRES_MUL;
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reg [31:0] rRES_MUL;
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always @(posedge clk_i) begin
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always @(posedge clk_i) begin
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rMUL_MA <= (MUL) ? rRES_MUL : 32'hX;
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rMUL_MA <= (MUL) ? rRES_MUL : 32'hX;
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rRES_MUL <= (rOPA * rOPB);
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rRES_MUL <= (MUL) ? (rOPA * rOPB) : 32'hX;
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end
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end
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// --- BARREL SHIFTER --------------------------------------
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/*
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// 1-stage
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BARREL SHIFTER
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This can be potentially made 2-stage to increase clock
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speed. Doesn't seem necessary at the moment as the critical path
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runs through the adder. */
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reg [31:0] rRES_BSF;
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reg [31:0] rRES_BSF;
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reg [31:0] xBSRL, xBSRA, xBSLL;
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reg [31:0] xBSRL, xBSRA, xBSLL;
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|
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// Infer a logical left barrel shifter.
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/* logical left barrel shifter */
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always @(/*AUTOSENSE*/rOPA or rOPB)
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always @(/*AUTOSENSE*/rOPA or rOPB)
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xBSLL <= rOPA << rOPB[4:0];
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xBSLL <= rOPA << rOPB[4:0];
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|
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// Infer a logical right barrel shifter.
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/* logical right barrel shifter */
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always @(/*AUTOSENSE*/rOPA or rOPB)
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always @(/*AUTOSENSE*/rOPA or rOPB)
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xBSRL <= rOPA >> rOPB[4:0];
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xBSRL <= rOPA >> rOPB[4:0];
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|
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// Infer a arithmetic right barrel shifter.
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/* arithmetic right barrel shifter */
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always @(/*AUTOSENSE*/rOPA or rOPB)
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always @(/*AUTOSENSE*/rOPA or rOPB)
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case (rOPB[4:0])
|
case (rOPB[4:0])
|
5'd00: xBSRA <= rOPA;
|
5'd00: xBSRA <= rOPA;
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5'd01: xBSRA <= {{(1){rOPA[31]}}, rOPA[31:1]};
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5'd01: xBSRA <= {{(1){rOPA[31]}}, rOPA[31:1]};
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5'd02: xBSRA <= {{(2){rOPA[31]}}, rOPA[31:2]};
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5'd02: xBSRA <= {{(2){rOPA[31]}}, rOPA[31:2]};
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| Line 243... |
Line 303... |
5'd29: xBSRA <= {{(29){rOPA[31]}}, rOPA[31:29]};
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5'd29: xBSRA <= {{(29){rOPA[31]}}, rOPA[31:29]};
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5'd30: xBSRA <= {{(30){rOPA[31]}}, rOPA[31:30]};
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5'd30: xBSRA <= {{(30){rOPA[31]}}, rOPA[31:30]};
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5'd31: xBSRA <= {{(31){rOPA[31]}}, rOPA[31]};
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5'd31: xBSRA <= {{(31){rOPA[31]}}, rOPA[31]};
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endcase // case (rOPB[4:0])
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endcase // case (rOPB[4:0])
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|
|
|
/* select the shift result (2nd stage) */
|
always @(/*AUTOSENSE*/rALT or xBSLL or xBSRA or xBSRL)
|
always @(/*AUTOSENSE*/rALT or xBSLL or xBSRA or xBSRL)
|
case (rALT[10:9])
|
case (rALT[10:9])
|
2'd0: rRES_BSF <= xBSRL;
|
2'd0: rRES_BSF <= xBSRL;
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2'd1: rRES_BSF <= xBSRA;
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2'd1: rRES_BSF <= xBSRA;
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2'd2: rRES_BSF <= xBSLL;
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2'd2: rRES_BSF <= xBSLL;
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default: rRES_BSF <= 32'hX;
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default: rRES_BSF <= 32'hX;
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endcase // case (rALT[10:9])
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endcase // case (rALT[10:9])
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// --- MSR REGISTER -----------------
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/*
|
|
MSR REGISTER
|
|
|
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Move data to the MSR or change due to break/returns. */
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|
|
reg xMSR_C;
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reg xMSR_C;
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|
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// C
|
// C
|
wire fMTS = (rOPC == 6'o45) & rIMM[14];
|
wire fMTS = (rOPC == 6'o45) & rIMM[14];
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wire fADDC = ({rOPC[5:4], rOPC[2]} == 3'o0);
|
wire fADDC = ({rOPC[5:4], rOPC[2]} == 3'o0);
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| Line 269... |
Line 334... |
3'o2: xMSR_C <= rRES_SFTC; // SHIFT
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3'o2: xMSR_C <= rRES_SFTC; // SHIFT
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3'o3: xMSR_C <= (fMTS) ? rOPA[2] : rMSR_C;
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3'o3: xMSR_C <= (fMTS) ? rOPA[2] : rMSR_C;
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3'o4: xMSR_C <= rMSR_C;
|
3'o4: xMSR_C <= rMSR_C;
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3'o5: xMSR_C <= rMSR_C;
|
3'o5: xMSR_C <= rMSR_C;
|
default: xMSR_C <= 1'hX;
|
default: xMSR_C <= 1'hX;
|
endcase
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endcase // case (rALU_OF)
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|
|
always @(posedge clk_i)
|
always @(posedge clk_i)
|
if (rst_i) begin
|
if (rst_i) begin
|
/*AUTORESET*/
|
/*AUTORESET*/
|
// Beginning of autoreset for uninitialized flops
|
// Beginning of autoreset for uninitialized flops
|
rMSR_C0 <= 1'h0;
|
rMSR_C0 <= 1'h0;
|
rMSR_C1 <= 1'h0;
|
rMSR_C1 <= 1'h0;
|
// End of automatics
|
// End of automatics
|
end else if (ena_i) begin
|
end else begin
|
if (pha_i)
|
if (pha_i & ena_i & rMSR_TXE)
|
rMSR_C1 <= #1 xMSR_C;
|
rMSR_C1 <= #1 xMSR_C;
|
else
|
|
rMSR_C0 <= #1 xMSR_C;
|
|
end
|
|
|
|
always @(posedge clk_i)
|
if (!pha_i & ena_i)
|
if (ena_i)
|
rMSR_C0 <= #1 xMSR_C;
|
rMSR_CL[pha_i] <= xMSR_C;
|
end // else: !if(rst_i)
|
|
|
// IE/BIP/BE
|
// IE/BIP/BE
|
wire fRTID = (rOPC == 6'o55) & rRD[0];
|
wire fRTID = (rOPC == 6'o55) & rRD[0];
|
wire fRTBD = (rOPC == 6'o55) & rRD[1];
|
wire fRTBD = (rOPC == 6'o55) & rRD[1];
|
wire fBRK = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA == 5'hC);
|
wire fBRK = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA == 5'hC);
|
| Line 302... |
Line 364... |
/*AUTORESET*/
|
/*AUTORESET*/
|
// Beginning of autoreset for uninitialized flops
|
// Beginning of autoreset for uninitialized flops
|
rMSR_BE <= 1'h0;
|
rMSR_BE <= 1'h0;
|
rMSR_BIP <= 1'h0;
|
rMSR_BIP <= 1'h0;
|
rMSR_IE <= 1'h0;
|
rMSR_IE <= 1'h0;
|
|
rMSR_TXE <= 1'h0;
|
// End of automatics
|
// End of automatics
|
end else if (ena_i) begin
|
end else if (ena_i) begin
|
|
|
|
// Interrupt enable (compatible)
|
rMSR_IE <= #1
|
rMSR_IE <= #1
|
(fINT) ? 1'b0 :
|
(fINT) ? 1'b0 :
|
(fRTID) ? 1'b1 :
|
(fRTID) ? 1'b1 :
|
(fMTS) ? rOPA[1] :
|
(fMTS) ? rOPA[1] :
|
rMSR_IE;
|
rMSR_IE;
|
|
|
|
// Break in progress (compatible)
|
rMSR_BIP <= #1
|
rMSR_BIP <= #1
|
(fBRK) ? 1'b1 :
|
(fBRK) ? 1'b1 :
|
(fRTBD) ? 1'b0 :
|
(fRTBD) ? 1'b0 :
|
(fMTS) ? rOPA[3] :
|
(fMTS) ? rOPA[3] :
|
rMSR_BIP;
|
rMSR_BIP;
|
|
|
|
// Forcibly assert dwb_cyc_o signal
|
rMSR_BE <= #1
|
rMSR_BE <= #1
|
(fMTS) ? rOPA[0] : rMSR_BE;
|
(fMTS) ? rOPA[0] : rMSR_BE;
|
end
|
|
|
|
|
// Enable the thread extension
|
|
rMSR_TXE <= #1
|
|
(fMTS) ? rOPA[28] & TXE : rMSR_TXE;
|
|
|
|
end // if (ena_i)
|
|
|
// --- RESULT SELECTOR -------------------------------------------
|
/*
|
// Selects results from functional units.
|
RESULTS
|
|
*/
|
|
|
// RESULT
|
// RESULT
|
always @(posedge clk_i)
|
always @(posedge clk_i)
|
if (rst_i) begin
|
if (rst_i) begin
|
/*AUTORESET*/
|
/*AUTORESET*/
|
| Line 346... |
Line 417... |
3'o5: rRES_EX <= #1 (BSF) ? rRES_BSF : 32'hX;
|
3'o5: rRES_EX <= #1 (BSF) ? rRES_BSF : 32'hX;
|
default: rRES_EX <= #1 32'hX;
|
default: rRES_EX <= #1 32'hX;
|
endcase // case (rALU_OF)
|
endcase // case (rALU_OF)
|
end // if (ena_i)
|
end // if (ena_i)
|
|
|
// --- DATA/FSL WISHBONE -----
|
/*
|
|
DATA/FSL WISHBONE
|
|
|
|
Asserts the data address as calculated by the adder and the
|
|
appropriate byte select lanes depending on the byte offset of the
|
|
address. It does not check for mis-aligned addresses. */
|
|
|
|
// TODO: Check for mis-alignment
|
|
|
always @(posedge clk_i)
|
always @(posedge clk_i)
|
if (rst_i) begin
|
if (rst_i) begin
|
/*AUTORESET*/
|
/*AUTORESET*/
|
// Beginning of autoreset for uninitialized flops
|
// Beginning of autoreset for uninitialized flops
|
| Line 359... |
Line 437... |
cwb_tga_o <= 2'h0;
|
cwb_tga_o <= 2'h0;
|
dwb_adr_o <= {(1+(DWB-1)-(2)){1'b0}};
|
dwb_adr_o <= {(1+(DWB-1)-(2)){1'b0}};
|
dwb_sel_o <= 4'h0;
|
dwb_sel_o <= 4'h0;
|
rSEL_MA <= 4'h0;
|
rSEL_MA <= 4'h0;
|
// End of automatics
|
// End of automatics
|
end else if (ena_i) begin
|
end else if (ena_i) begin // if (rst_i)
|
rSEL_MA <= #1 dwb_sel_o;
|
rSEL_MA <= #1 dwb_sel_o;
|
|
|
dwb_adr_o <= #1 wADD[DWB-1:2];
|
dwb_adr_o <= #1 wADD[DWB-1:2];
|
case (rOPC[1:0])
|
case (rOPC[1:0])
|
2'o0: case (wADD[1:0]) // 8'bit
|
2'o0: case (wADD[1:0]) // 8'bit
|
| Line 388... |
Line 466... |
initial begin
|
initial begin
|
for (r=0; r<TXE; r=r+1) begin
|
for (r=0; r<TXE; r=r+1) begin
|
rMSR_CL[r] <= $random;
|
rMSR_CL[r] <= $random;
|
end
|
end
|
end
|
end
|
|
|
// synopsys translate_on
|
// synopsys translate_on
|
|
|
endmodule // aeMB2_aslu
|
endmodule // aeMB2_aslu
|
|
|
/* $Log: not supported by cvs2svn $ */
|
|
No newline at end of file
|
No newline at end of file
|
|
/* $Log: not supported by cvs2svn $
|
|
/* Revision 1.1 2007/12/11 00:43:17 sybreon
|
|
/* initial import
|
|
/* */
|
No newline at end of file
|
No newline at end of file
|
