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/* $Id: aeMB2_aslu.v,v 1.2 2007-12-12 19:16:59 sybreon Exp $
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/* $Id: aeMB2_aslu.v,v 1.3 2007-12-13 20:12:11 sybreon Exp $
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**
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**
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** AEMB2 INTEGER ARITHMETIC SHIFT LOGIC UNIT
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** AEMB2 INTEGER ARITHMETIC SHIFT LOGIC UNIT
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**
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**
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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**
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**
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*/
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*/
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module aeMB2_aslu (/*AUTOARG*/
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module aeMB2_aslu (/*AUTOARG*/
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// Outputs
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// Outputs
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dwb_adr_o, dwb_sel_o, rSEL_MA, cwb_adr_o, cwb_tga_o, cwb_sel_o,
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dwb_adr_o, dwb_sel_o, rSEL_MA, cwb_adr_o, cwb_tga_o, cwb_sel_o,
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rMUL_MA, rRES_MA, rRES_EX, rMSR_IE, rMSR_BE, rMSR_TXE, rMSR_BIP,
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iwb_tga_o, dwb_tga_o, rMUL_MA, rRES_MA, rRES_EX, rMSR_IE, rMSR_BE,
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rMSR_BIP,
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// Inputs
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// Inputs
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rIMM_OF, rALU_OF, rOPC_OF, rOPC_IF, rRA_OF, rRD_OF, rOPA_OF,
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rIMM_OF, rALU_OF, rOPC_OF, rOPC_IF, rRA_OF, rRD_OF, rOPA_OF,
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rOPB_OF, pha_i, clk_i, rst_i, ena_i
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rOPB_OF, pha_i, clk_i, rst_i, ena_i
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);
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);
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Line 45... |
// FSL
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// FSL
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output [6:2] cwb_adr_o;
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output [6:2] cwb_adr_o;
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output [1:0] cwb_tga_o;
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output [1:0] cwb_tga_o;
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output [3:0] cwb_sel_o;
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output [3:0] cwb_sel_o;
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// CACHE ENABLE
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output iwb_tga_o,
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dwb_tga_o;
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// PIPELINE
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// PIPELINE
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output [31:0] rMUL_MA;
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output [31:0] rMUL_MA;
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output [31:0] rRES_MA,
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output [31:0] rRES_MA,
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rRES_EX;
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rRES_EX;
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output rMSR_IE,
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output rMSR_IE,
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rMSR_BE,
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rMSR_BE,
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rMSR_TXE,
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//rMSR_TXE,
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//rMSR_DCE,
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//rMSR_ICE,
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rMSR_BIP;
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rMSR_BIP;
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input [15:0] rIMM_OF;
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input [15:0] rIMM_OF;
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input [2:0] rALU_OF;
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input [2:0] rALU_OF;
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input [5:0] rOPC_OF,
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input [5:0] rOPC_OF,
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| Line 78... |
Line 85... |
reg [6:2] cwb_adr_o;
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reg [6:2] cwb_adr_o;
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reg [3:0] cwb_sel_o;
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reg [3:0] cwb_sel_o;
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reg [1:0] cwb_tga_o;
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reg [1:0] cwb_tga_o;
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reg [DWB-1:2] dwb_adr_o;
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reg [DWB-1:2] dwb_adr_o;
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reg [3:0] dwb_sel_o;
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reg [3:0] dwb_sel_o;
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reg dwb_tga_o;
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reg iwb_tga_o;
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reg rMSR_BE;
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reg rMSR_BE;
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reg rMSR_BIP;
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reg rMSR_BIP;
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reg rMSR_IE;
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reg rMSR_IE;
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reg rMSR_TXE;
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reg [31:0] rMUL_MA;
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reg [31:0] rMUL_MA;
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reg [31:0] rRES_EX;
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reg [31:0] rRES_EX;
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reg [31:0] rRES_MA;
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reg [31:0] rRES_MA;
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reg [3:0] rSEL_MA;
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reg [3:0] rSEL_MA;
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// End of automatics
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// End of automatics
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reg rMSR_C0,
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reg rMSR_C0,
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rMSR_C1,
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rMSR_C1,
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rMSR_C,
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rMSR_CL[0:1];
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rMSR_CL[0:1];
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wire [4:0] rRD = rRD_OF;
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wire [4:0] rRD = rRD_OF;
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wire [31:0] rOPA = rOPA_OF;
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wire [31:0] rOPA = rOPA_OF;
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| Line 102... |
Line 111... |
wire [4:0] rRA = rRA_OF;
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wire [4:0] rRA = rRA_OF;
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wire [15:0] rIMM = rIMM_OF;
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wire [15:0] rIMM = rIMM_OF;
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wire [10:0] rALT = rIMM_OF[10:0];
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wire [10:0] rALT = rIMM_OF[10:0];
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/*
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/*
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MSR REGISTER
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We should keep common configuration bits in the lower 16-bits of
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the MSR in order to avoid using the IMMI instruction.
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MSR bits
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31 - CC (carry copy)
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10 - HTE (hardware thread enabled)
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9 - PHA (current phase)
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8 - TXE (enable threads)
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7 - DCE (data cache enable)
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5 - ICE (instruction cache enable)
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4 - FSL (FSL available)
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3 - BIP (break in progress)
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2 - C (carry flag)
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1 - IE (interrupt enable)
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0 - BE (bus-lock enable)
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*/
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wire [31:0] wMSR = {rMSR_C, // MSR_CC
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20'd0, // Reserved
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TXE[0], // (PVR)
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pha_i, // (EIP)
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TXE[0], // (EE)
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dwb_tga_o, // MSR_DCE
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1'b0, // reserved for DZ
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iwb_tga_o, // MSR_ICE
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FSL[0], // GET/PUT available
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rMSR_BIP, // MSR_BIP
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rMSR_C, // MSR_C
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rMSR_IE, // MSR_IE
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rMSR_BE}; // MSR_BE
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/*
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C SELECTOR
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C SELECTOR
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Preselects the C in the OF stage to speed things up. */
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Preselects the C to speed things up. */
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// TODO: Optimise
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// TODO: Optimise
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wire wMSR_CX, wMSR_C;
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wire wMSR_CX, wMSR_C;
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assign wMSR_CX = (pha_i) ? rMSR_C0 :
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assign wMSR_CX = (pha_i) ? rMSR_C0 : rMSR_C1;
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(TXE) ? rMSR_C1 : 1'bX;
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assign wMSR_C = (rOPC_IF == 6'o44) & wMSR_CX | // SRX
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assign wMSR_C = (rOPC_IF == 6'o44) & wMSR_CX | // SRX
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(rOPC_IF[5:4] == 2'o0) & rOPC_IF[1] & wMSR_CX | // ADDC/RSUBC
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(rOPC_IF[5:4] == 2'o0) & rOPC_IF[1] & wMSR_CX | // ADDC/RSUBC
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(rOPC_IF[5:4] == 2'o0) & (rOPC_IF[1:0] == 2'o1); // RSUB
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(rOPC_IF[5:4] == 2'o0) & (rOPC_IF[1:0] == 2'o1); // RSUB
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reg rMSR_C;
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always @(posedge clk_i)
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always @(posedge clk_i)
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if (rst_i) begin
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if (rst_i) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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rMSR_C <= 1'h0;
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rMSR_C <= 1'h0;
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Line 248... |
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always @(/*AUTOSENSE*/rIMM or rMSR_C or rOPA)
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always @(/*AUTOSENSE*/rIMM or rMSR_C or rOPA)
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rRES_SFTC <= (&rIMM[6:5]) ? rMSR_C : rOPA[0];
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rRES_SFTC <= (&rIMM[6:5]) ? rMSR_C : rOPA[0];
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/*
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/*
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MOVE FROM SPECIAL
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MOVER
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MSR bits
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31 - CC (carry copy)
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30 - PHA (current phase)
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29 - TXE (enable second thread)
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3 - BIP (break in progress)
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2 - C (carry flag)
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1 - IE (interrupt enable)
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0 - BE (bus-lock enable)
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*/
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*/
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wire wTXE = (TXE) ? 1'b1 : 1'b0;
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wire [31:0] wMSR = {rMSR_C, // MSR_CC
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pha_i, // Current phase
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rMSR_TXE, // Thread Execution Enabled
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wTXE,
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4'h0, // Reserved
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8'hAE, // Vendor
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8'h32, // Version
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4'h0, // Reserved
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rMSR_BIP, // MSR_BIP
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rMSR_C, // MSR_C
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rMSR_IE, // MSR_IE
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rMSR_BE}; // MSR_BE
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wire fMFSR = (rOPC == 6'o45) & !rIMM[14] & rIMM[0];
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wire fMFSR = (rOPC == 6'o45) & !rIMM[14] & rIMM[0];
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wire fMFPC = (rOPC == 6'o45) & !rIMM[14] & !rIMM[0];
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wire fMFPC = (rOPC == 6'o45) & !rIMM[14] & !rIMM[0];
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reg [31:0] rRES_MOV;
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reg [31:0] rRES_MOV;
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always @(/*AUTOSENSE*/fMFSR or rOPA or rOPB or rRA or wMSR)
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always @(/*AUTOSENSE*/fMFSR or rOPA or rOPB or rRA or wMSR)
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rRES_MOV <= (fMFSR) ? wMSR :
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case ({fMFSR, rRA[3]})
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//(fMFPC) ? rOPA :
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2'o0: rRES_MOV <= rOPA; // MFS rpc
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(rRA[3]) ? rOPB :
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2'o1: rRES_MOV <= rOPB; // BRA
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rOPA;
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2'o2: rRES_MOV <= wMSR; // MFS rmsr
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default: rRES_MOV <= 32'hX;
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endcase // case ({fMFSR, rRA[3]})
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//rRES_MOV <= (fMFSR) ? wMSR : //(fMFPC) ? rOPA : (rRA[3]) ? rOPB : rOPA;
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/*
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/*
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MULTIPLIER
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MULTIPLIER
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Implemented as a 2-stage multiplier in order to increase clock
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Implemented as a 2-stage multiplier in order to increase clock
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speed. */
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speed. */
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reg [31:0] rRES_MUL;
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reg [31:0] rRES_MUL;
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always @(posedge clk_i) begin
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always @(posedge clk_i) begin
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rMUL_MA <= (MUL) ? rRES_MUL : 32'hX;
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rMUL_MA <= #1 rRES_MUL;
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rRES_MUL <= (MUL) ? (rOPA * rOPB) : 32'hX;
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rRES_MUL <= #1 (rOPA * rOPB);
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end
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end
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/*
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/*
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BARREL SHIFTER
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BARREL SHIFTER
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This can be potentially made 2-stage to increase clock
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This can be potentially made 2-stage if it is a
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speed. Doesn't seem necessary at the moment as the critical path
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bottleneck. Doesn't seem necessary at the moment as the critical
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runs through the adder. */
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path runs through the adder. */
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reg [31:0] rRES_BSF;
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reg [31:0] rRES_BSF;
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reg [31:0] xBSRL, xBSRA, xBSLL;
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reg [31:0] xBSRL, xBSRA, xBSLL;
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/* logical left barrel shifter */
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/* logical left barrel shifter */
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| Line 312... |
Line 340... |
2'd1: rRES_BSF <= xBSRA;
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2'd1: rRES_BSF <= xBSRA;
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2'd2: rRES_BSF <= xBSLL;
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2'd2: rRES_BSF <= xBSLL;
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default: rRES_BSF <= 32'hX;
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default: rRES_BSF <= 32'hX;
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endcase // case (rALT[10:9])
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endcase // case (rALT[10:9])
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/*
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/*
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MSR REGISTER
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MSR REGISTER
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Move data to the MSR or change due to break/returns. */
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Move data to the MSR or change due to break/returns. */
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| Line 343... |
Line 370... |
/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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rMSR_C0 <= 1'h0;
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rMSR_C0 <= 1'h0;
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rMSR_C1 <= 1'h0;
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rMSR_C1 <= 1'h0;
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// End of automatics
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// End of automatics
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end else begin
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end else if (ena_i) begin
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if (pha_i & ena_i & rMSR_TXE)
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if (pha_i)
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rMSR_C1 <= #1 xMSR_C;
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rMSR_C1 <= #1 xMSR_C;
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else
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if (!pha_i & ena_i)
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rMSR_C0 <= #1 xMSR_C;
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rMSR_C0 <= #1 xMSR_C;
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end // else: !if(rst_i)
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end // else: !if(rst_i)
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// IE/BIP/BE
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// IE/BIP/BE
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wire fRTID = (rOPC == 6'o55) & rRD[0];
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wire fRTID = (rOPC == 6'o55) & rRD[0];
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| Line 361... |
Line 387... |
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always @(posedge clk_i)
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always @(posedge clk_i)
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if (rst_i) begin
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if (rst_i) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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dwb_tga_o <= 1'h0;
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iwb_tga_o <= 1'h0;
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rMSR_BE <= 1'h0;
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rMSR_BE <= 1'h0;
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rMSR_BIP <= 1'h0;
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rMSR_BIP <= 1'h0;
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rMSR_IE <= 1'h0;
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rMSR_IE <= 1'h0;
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rMSR_TXE <= 1'h0;
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// End of automatics
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// End of automatics
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end else if (ena_i) begin
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end else if (ena_i) begin
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// Interrupt enable (compatible)
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// Interrupt enable (compatible)
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rMSR_IE <= #1
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rMSR_IE <= #1
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| Line 387... |
Line 414... |
// Forcibly assert dwb_cyc_o signal
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// Forcibly assert dwb_cyc_o signal
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rMSR_BE <= #1
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rMSR_BE <= #1
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(fMTS) ? rOPA[0] : rMSR_BE;
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(fMTS) ? rOPA[0] : rMSR_BE;
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// Enable the thread extension
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// Enable the thread extension
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rMSR_TXE <= #1
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//rMSR_TXE <= #1 TXE[0];
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(fMTS) ? rOPA[28] & TXE : rMSR_TXE;
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// Enable the caches
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dwb_tga_o <= #1 (fMTS) ?
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rOPA[7] :
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dwb_tga_o;
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iwb_tga_o <= #1 (fMTS) ?
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rOPA[5] :
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iwb_tga_o;
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end // if (ena_i)
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end // if (ena_i)
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/*
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/*
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RESULTS
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RESULTS
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| Line 458... |
Line 492... |
{cwb_adr_o, cwb_tga_o} <= #1 {rIMM_OF[4:0], rIMM_OF[15:14]};
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{cwb_adr_o, cwb_tga_o} <= #1 {rIMM_OF[4:0], rIMM_OF[15:14]};
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cwb_sel_o <= #1 {(4){ &rOPC[1:0]}};
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cwb_sel_o <= #1 {(4){ &rOPC[1:0]}};
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end // if (ena_i)
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end // if (ena_i)
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// synopsys translate_off
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integer r;
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initial begin
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for (r=0; r<TXE; r=r+1) begin
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rMSR_CL[r] <= $random;
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end
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end
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// synopsys translate_on
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endmodule // aeMB2_aslu
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endmodule // aeMB2_aslu
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/* $Log: not supported by cvs2svn $
|
/* $Log: not supported by cvs2svn $
|
|
/* Revision 1.2 2007/12/12 19:16:59 sybreon
|
|
/* Minor optimisations (~10% faster)
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/*
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/* Revision 1.1 2007/12/11 00:43:17 sybreon
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/* Revision 1.1 2007/12/11 00:43:17 sybreon
|
/* initial import
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/* initial import
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/* */
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/* */
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No newline at end of file
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No newline at end of file
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