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/* $Id: aeMB2_aslu.v,v 1.4 2007-12-13 21:25:41 sybreon Exp $
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/* $Id: aeMB2_aslu.v,v 1.5 2007-12-16 03:25:37 sybreon Exp $
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**
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**
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** AEMB2 INTEGER ARITHMETIC SHIFT LOGIC UNIT
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** AEMB2 INTEGER ARITHMETIC SHIFT LOGIC UNIT
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**
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**
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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**
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**
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3'o0: rRES_SLM <= #1 rOPA | rOPB;
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3'o0: rRES_SLM <= #1 rOPA | rOPB;
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3'o1: rRES_SLM <= #1 rOPA & rOPB;
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3'o1: rRES_SLM <= #1 rOPA & rOPB;
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3'o2: rRES_SLM <= #1 rOPA ^ rOPB;
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3'o2: rRES_SLM <= #1 rOPA ^ rOPB;
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3'o3: rRES_SLM <= #1 rOPA & ~rOPB;
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3'o3: rRES_SLM <= #1 rOPA & ~rOPB;
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3'o4: case (rIMM[6:5])
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3'o4: case (rIMM[6:5])
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2'o0: rRES_SLM <= {rOPA[31],rOPA[31:1]}; // SRA
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2'o0: rRES_SLM <= #1 {rOPA[31],rOPA[31:1]}; // SRA
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2'o1: rRES_SLM <= {rMSR_C,rOPA[31:1]}; // SRC
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2'o1: rRES_SLM <= #1 {rMSR_C,rOPA[31:1]}; // SRC
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2'o2: rRES_SLM <= {1'b0,rOPA[31:1]}; // SRL
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2'o2: rRES_SLM <= #1 {1'b0,rOPA[31:1]}; // SRL
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2'o3: rRES_SLM <= (rIMM[0]) ?
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2'o3: rRES_SLM <= #1 (rIMM[0]) ?
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{{(16){rOPA[15]}}, rOPA[15:0]} : // SEXT16
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{{(16){rOPA[15]}}, rOPA[15:0]} : // SEXT16
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{{(24){rOPA[7]}}, rOPA[7:0]}; // SEXT8
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{{(24){rOPA[7]}}, rOPA[7:0]}; // SEXT8
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endcase // case (rIMM[6:5])
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endcase // case (rIMM[6:5])
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3'o5: case ({fMFSR, rRA[3]})
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3'o5: case ({fMFSR, rRA[3]})
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2'o0: rRES_SLM <= rOPA; // MFS rpc
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2'o0: rRES_SLM <= #1 rOPA; // MFS rpc
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2'o1: rRES_SLM <= rOPB; // BRA
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2'o1: rRES_SLM <= #1 rOPB; // BRA
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2'o2: rRES_SLM <= wMSR; // MFS rmsr
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2'o2: rRES_SLM <= #1 wMSR; // MFS rmsr
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default: rRES_MOV <= 32'hX;
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default: rRES_MOV <= #1 32'hX;
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endcase // case ({fMFSR, rRA[3]})
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endcase // case ({fMFSR, rRA[3]})
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3'o6: rRES_SLM <= rOPB;
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3'o6: rRES_SLM <= #1 rOPB;
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default: rRES_SLM <= 32'hX;
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default: rRES_SLM <= #1 32'hX;
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endcase // case (rOPC[2:0])
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endcase // case (rOPC[2:0])
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/*
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/*
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MULTIPLIER
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MULTIPLIER
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3'o5: rRES_EX <= #1 (BSF) ? rRES_BSF : 32'hX;
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3'o5: rRES_EX <= #1 (BSF) ? rRES_BSF : 32'hX;
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default: rRES_EX <= #1 32'hX;
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default: rRES_EX <= #1 32'hX;
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endcase // case (rALU_OF)
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endcase // case (rALU_OF)
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*/
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*/
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case (rALU_OF[1:0])
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case (rALU_OF[1:0])
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//case (rOPC[5:4])
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2'o0: rRES_EX <= #1 rRES_ADD;
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2'o0: rRES_EX <= #1 rRES_ADD;
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2'o1: rRES_EX <= #1 rRES_SLM;
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2'o2: rRES_EX <= #1 rRES_SLM;
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2'o2: rRES_EX <= #1 (BSF) ? rRES_BSF : 32'hX;
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2'o1: rRES_EX <= #1 (BSF) ? rRES_BSF : 32'hX;
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default: rRES_EX <= #1 32'hX;
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default: rRES_EX <= #1 32'hX;
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endcase // case (rALU_OF[1:0])
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endcase // case (rALU_OF[1:0])
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end // if (ena_i)
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end // if (ena_i)
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// C
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// C
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wire fMTS = (rOPC == 6'o45) & rIMM[14];
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wire fMTS = (rOPC == 6'o45) & rIMM[14];
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wire fADDC = ({rOPC[5:4], rOPC[2]} == 3'o0);
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wire fADDC = ({rOPC[5:4], rOPC[2]} == 3'o0);
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always @(/*AUTOSENSE*/fADDC or rALU_OF or rIMM or rMSR_C or rOPC
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always @(/*AUTOSENSE*/fADDC or rIMM or rMSR_C or rOPC or rRES_ADDC
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or rRES_ADDC or rRES_SFTC)
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or rRES_SFTC)
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case (rALU_OF[1:0])
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//case (rALU_OF[1:0])
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case (rOPC[5:4])
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3'o0: xMSR_C <= (fADDC) ? rRES_ADDC : rMSR_C; // ADD/SUB
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3'o0: xMSR_C <= (fADDC) ? rRES_ADDC : rMSR_C; // ADD/SUB
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3'o1: case (rOPC[2:0])
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3'o2: case (rOPC[2:0])
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3'o5: xMSR_C <= (rIMM[14]) ? rOPC[2] : rMSR_C; // MTS
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3'o5: xMSR_C <= (rIMM[14]) ? rOPC[2] : rMSR_C; // MTS
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3'o4: xMSR_C <= (&rIMM[6:5]) ? rMSR_C : rRES_SFTC; // SRX
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3'o4: xMSR_C <= (&rIMM[6:5]) ? rMSR_C : rRES_SFTC; // SRX
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default: xMSR_C <= rMSR_C;
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default: xMSR_C <= rMSR_C;
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endcase // case (rOPC[2:0])
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endcase // case (rOPC[2:0])
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default: xMSR_C <= rMSR_C;
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default: xMSR_C <= rMSR_C;
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endcase // case (rALU_OF)
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endcase // case (rOPC[5:4])
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/*
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/*
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case (rALU_OF)
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case (rALU_OF)
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3'o0: xMSR_C <= (fADDC) ? rRES_ADDC : rMSR_C;
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3'o0: xMSR_C <= (fADDC) ? rRES_ADDC : rMSR_C;
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3'o1: xMSR_C <= rMSR_C; // LOGIC
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3'o1: xMSR_C <= rMSR_C; // LOGIC
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end else if (ena_i) begin
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end else if (ena_i) begin
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if (pha_i)
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if (pha_i)
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rMSR_C1 <= #1 xMSR_C;
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rMSR_C1 <= #1 xMSR_C;
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else
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else
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rMSR_C0 <= #1 xMSR_C;
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rMSR_C0 <= #1 xMSR_C;
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end // else: !if(rst_i)
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end
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// IE/BIP/BE
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// IE/BIP/BE
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wire fRTID = (rOPC == 6'o55) & rRD[0];
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wire fRTID = (rOPC == 6'o55) & rRD[0];
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wire fRTBD = (rOPC == 6'o55) & rRD[1];
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wire fRTBD = (rOPC == 6'o55) & rRD[1];
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wire fBRK = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA == 5'hC);
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wire fBRK = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA == 5'hC);
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end // if (ena_i)
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end // if (ena_i)
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endmodule // aeMB2_aslu
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endmodule // aeMB2_aslu
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/* $Log: not supported by cvs2svn $
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/* $Log: not supported by cvs2svn $
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/* Revision 1.4 2007/12/13 21:25:41 sybreon
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/* Further optimisations (speed + size).
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/*
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/* Revision 1.3 2007/12/13 20:12:11 sybreon
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/* Revision 1.3 2007/12/13 20:12:11 sybreon
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/* Code cleanup + minor speed regression.
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/* Code cleanup + minor speed regression.
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/*
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/*
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/* Revision 1.2 2007/12/12 19:16:59 sybreon
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/* Revision 1.2 2007/12/12 19:16:59 sybreon
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/* Minor optimisations (~10% faster)
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/* Minor optimisations (~10% faster)
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