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/* $Id: aeMB2_aslu.v,v 1.6 2007-12-16 20:38:06 sybreon Exp $
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/* $Id: aeMB2_aslu.v,v 1.7 2007-12-17 12:53:27 sybreon Exp $
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**
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**
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** AEMB2 INTEGER ARITHMETIC SHIFT LOGIC UNIT
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** AEMB2 INTEGER ARITHMETIC SHIFT LOGIC UNIT
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**
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**
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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**
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**
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// End of automatics
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// End of automatics
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reg rMSR_C0,
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reg rMSR_C0,
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rMSR_C1,
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rMSR_C1,
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rMSR_C,
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rMSR_C,
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rMSR_CC,
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rMSR_CL[0:1];
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rMSR_CL[0:1];
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wire [4:0] rRD = rRD_OF;
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wire [4:0] rRD = rRD_OF;
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wire [31:0] rOPA = rOPA_OF;
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wire [31:0] rOPA = rOPA_OF;
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// TODO: Optimise
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// TODO: Optimise
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wire wMSR_CX, wMSR_C;
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wire wMSR_CX, wMSR_C;
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assign wMSR_CX = (pha_i) ? rMSR_C0 : rMSR_C1;
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assign wMSR_CX = (pha_i) ? rMSR_C0 : rMSR_C1;
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assign wMSR_C = (rOPC_IF == 6'o44) & wMSR_CX | // SRX
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assign wMSR_C = (rOPC_IF == 6'o44) & wMSR_CX | // SRX
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(rOPC_IF[5:4] == 2'o0) & rOPC_IF[1] & wMSR_CX | // ADDC/RSUBC
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(rOPC_IF[5:4] == 2'o0) & rOPC_IF[1] & wMSR_CX | // ADDC/RSUBC
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(rOPC_IF[5:4] == 2'o0) & (rOPC_IF[1:0] == 2'o1); // RSUB
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(rOPC_IF[5:4] == 2'o0) & (rOPC_IF[1:0] == 2'o1); // RSUB
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/*
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assign wMSR_C = ((rOPC_IF[5:4] == 2'o0) & (rOPC_OF[1:0] == 2'o1)) ? 1'b1 : // RSUB = 1
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((rOPC_IF[5:4] == 2'o0) & (rOPC_OF[1:0] == 2'o0)) ? 1'b0 : // ADD = 0
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wMSR_CX;
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*/
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always @(posedge clk_i)
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always @(posedge clk_i)
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if (rst_i) begin
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if (rst_i) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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rMSR_C <= 1'h0;
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rMSR_C <= 1'h0;
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rMSR_CC <= 1'h0;
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// End of automatics
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// End of automatics
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end else if (ena_i) begin
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end else if (ena_i) begin
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rMSR_C <= #1 wMSR_C;
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rMSR_C <= #1 wMSR_CX;
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rMSR_CC <= #1 wMSR_C;
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end
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end
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/*
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/*
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ADD/SUB SELECTOR
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ADD/SUB SELECTOR
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wire wCMPF = (rIMM[1]) ? wCMPU :
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wire wCMPF = (rIMM[1]) ? wCMPU :
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((wCMPU & ~(rOPB[31] ^ rOPA[31])) | (rOPB[31] & ~rOPA[31]));
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((wCMPU & ~(rOPB[31] ^ rOPA[31])) | (rOPB[31] & ~rOPA[31]));
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assign {wCMPC,wCMP} = {wSUBC,wCMPF,wSUB[30:0]};
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assign {wCMPC,wCMP} = {wSUBC,wCMPF,wSUB[30:0]};
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assign wOPX = (rOPC[0] & !rOPC[5]) ? ~rOPA : rOPA ;
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assign wOPX = (rOPC[0] & !rOPC[5]) ? ~rOPA : rOPA ;
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//assign wOPC = ((wMSR_C & rOPC[1]) | (rOPC[0] & !rOPC[1])) & (!rOPC[5] & ~&rOPC[5:4]);
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//assign wOPC = ((rMSR_C & rOPC[1]) | (rOPC[0] & !rOPC[1])) & (!rOPC[5] & ~&rOPC[5:4]);
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assign wOPC = rMSR_C;
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assign wOPC = rMSR_CC;
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assign {wSUBC,wSUB} = {wADDC,wADD};
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assign {wSUBC,wSUB} = {wADDC,wADD};
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assign {wADDC,wADD} = (rOPB + wOPX) + wOPC;
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assign {wADDC,wADD} = (rOPB + wOPX) + wOPC;
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reg rRES_ADDC;
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reg rRES_ADDC;
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reg [31:0] rRES_ADD;
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reg [31:0] rRES_ADD;
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always @(rIMM or rOPC or wADD or wADDC or wCMP
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always @(rIMM or rOPC or wADD or wADDC or wCMP
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or wCMPC or wSUB or wSUBC)
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or wCMPC or wSUB or wSUBC)
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case ({rOPC[3],rOPC[0],rIMM[0]})
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case ({rOPC[3],rOPC[0],rIMM[0]})
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4'h2, 4'h6, 4'h7: {rRES_ADDC,rRES_ADD} <= #1 {~wSUBC,wSUB}; // SUB
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4'h2, 4'h6, 4'h7: {rRES_ADDC,rRES_ADD} <= #1 {wSUBC,wSUB}; // SUB
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4'h3: {rRES_ADDC,rRES_ADD} <= #1 {~wCMPC,wCMP}; // CMP
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4'h3: {rRES_ADDC,rRES_ADD} <= #1 {wCMPC,wCMP}; // CMP
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default: {rRES_ADDC,rRES_ADD} <= #1 {wADDC,wADD};
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default: {rRES_ADDC,rRES_ADD} <= #1 {wADDC,wADD};
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endcase // case ({rOPC[3],rOPC[0],rIMM[0]})
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endcase // case ({rOPC[3],rOPC[0],rIMM[0]})
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/*
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/*
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LOGIC
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LOGIC
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or rRES_ADDC or rRES_SFTC)
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or rRES_ADDC or rRES_SFTC)
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case (rALU_OF[1:0])
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case (rALU_OF[1:0])
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//case (rOPC[5:4])
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//case (rOPC[5:4])
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3'o0: xMSR_C <= (fADDC) ? rRES_ADDC : rMSR_C; // ADD/SUB
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3'o0: xMSR_C <= (fADDC) ? rRES_ADDC : rMSR_C; // ADD/SUB
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3'o2: case (rOPC[2:0])
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3'o2: case (rOPC[2:0])
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3'o5: xMSR_C <= (rIMM[14]) ? rOPC[2] : rMSR_C; // MTS
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3'o5: xMSR_C <= (rIMM[14]) ? rOPA[2] : rMSR_C; // MTS
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3'o4: xMSR_C <= (&rIMM[6:5]) ? rMSR_C : rRES_SFTC; // SRX
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3'o4: xMSR_C <= (&rIMM[6:5]) ? rMSR_C : rRES_SFTC; // SRX
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default: xMSR_C <= rMSR_C;
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default: xMSR_C <= rMSR_C;
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endcase // case (rOPC[2:0])
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endcase // case (rOPC[2:0])
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default: xMSR_C <= rMSR_C;
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default: xMSR_C <= rMSR_C;
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endcase // case (rOPC[5:4])
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endcase // case (rOPC[5:4])
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end // if (ena_i)
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end // if (ena_i)
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endmodule // aeMB2_aslu
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endmodule // aeMB2_aslu
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/* $Log: not supported by cvs2svn $
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/* $Log: not supported by cvs2svn $
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/* Revision 1.6 2007/12/16 20:38:06 sybreon
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/* Minor optimisations.
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/*
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/* Revision 1.5 2007/12/16 03:25:37 sybreon
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/* Revision 1.5 2007/12/16 03:25:37 sybreon
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/* Some optimisations.
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/* Some optimisations.
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/*
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/*
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/* Revision 1.4 2007/12/13 21:25:41 sybreon
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/* Revision 1.4 2007/12/13 21:25:41 sybreon
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/* Further optimisations (speed + size).
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/* Further optimisations (speed + size).
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