OpenCores

Rev 80	Rev 81
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`/* $Id: aeMB2_bpcu.v,v 1.2 2007-12-12 19:16:59 sybreon Exp $`	`/* $Id: aeMB2_bpcu.v,v 1.3 2007-12-13 20:12:11 sybreon Exp $`
`**`	`**`
`** AEMB2 BRANCH/PROGRAMME COUNTER`	`** AEMB2 BRANCH/PROGRAMME COUNTER`
`**`	`**`
`** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>`	`** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>`
`**`	`**`
Line 24...	Line 24...
`// Outputs`	`// Outputs`
`iwb_adr_o, rPC_MA, rPC_IF, rIMM_IF, rALT_IF, rOPC_IF, rRD_IF,`	`iwb_adr_o, rPC_MA, rPC_IF, rIMM_IF, rALT_IF, rOPC_IF, rRD_IF,`
`rRA_IF, rRB_IF, rBRA,`	`rRA_IF, rRB_IF, rBRA,`
`// Inputs`	`// Inputs`
`iwb_dat_i, iwb_ack_i, rOPX_OF, rOPC_OF, rRA_OF, rRD_OF, rRES_EX,`	`iwb_dat_i, iwb_ack_i, rOPX_OF, rOPC_OF, rRA_OF, rRD_OF, rRES_EX,`
`rRD_EX, rOPD_EX, rMSR_TXE, clk_i, rst_i, ena_i, pha_i`	`rRD_EX, rOPD_EX, clk_i, rst_i, ena_i, pha_i`
`);`	`);`
`parameter IWB = 32;`	`parameter IWB = 32;`
`parameter TXE = 1;`	`parameter TXE = 1;`

`// IWB`	`// IWB`
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`// MEMORY HAZARD DETECTION`	`// MEMORY HAZARD DETECTION`
`input [4:0] rRD_EX; ///< RD`	`input [4:0] rRD_EX; ///< RD`
`input [2:0] rOPD_EX; ///< data register source (ALU, MEM/FSL, PC)`	`input [2:0] rOPD_EX; ///< data register source (ALU, MEM/FSL, PC)`

`// SYSTEM`	`// SYSTEM`
`input rMSR_TXE;`
`input clk_i,`	`input clk_i,`
`rst_i,`	`rst_i,`
`ena_i,`	`ena_i,`
`pha_i;`	`pha_i;`

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`reg [31:2] rPC, // PC`	`reg [31:2] rPC, // PC`
`rPC0, rPC1,// register based`	`rPC0, rPC1,// register based`
`rPCL[0:1]; // LUT based`	`rPCL[0:1]; // LUT based`

`wire [31:2] wPCNXT = (pha_i) ? rPC0 : (TXE) ? rPC1 : 30'hX;`	`wire [31:2] wPCNXT = (pha_i) ? rPC0 : rPC1;`
`wire [31:2] wPCINC = (rPC + 1);`	`wire [31:2] wPCINC = (rPC + 1);`

`/* Check for RW data hazard */`	`/* Check for RW data hazard */`
`// TODO: Optimise`	`// TODO: Optimise`

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`/AUTORESET/`	`/AUTORESET/`
`// Beginning of autoreset for uninitialized flops`	`// Beginning of autoreset for uninitialized flops`
`rPC0 <= 30'h0;`	`rPC0 <= 30'h0;`
`rPC1 <= 30'h0;`	`rPC1 <= 30'h0;`
`// End of automatics`	`// End of automatics`
`end else begin`	`end else if (ena_i) begin`
`if (pha_i & ena_i & rMSR_TXE) rPC1 <= #1 wPCINC;`	`if (pha_i)`
`if (!pha_i & ena_i) rPC0 <= #1 wPCINC;`	`rPC1 <= #1 wPCINC;`
	`else`
	`rPC0 <= #1 wPCINC;`
`end`	`end`

`/*`	`/*`
`INSTRUCTION LATCH`	`INSTRUCTION LATCH`

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`end`	`end`

`endmodule // aeMB2_bpcu`	`endmodule // aeMB2_bpcu`

`/* $Log: not supported by cvs2svn $`	`/* $Log: not supported by cvs2svn $`
	`/* Revision 1.2 2007/12/12 19:16:59 sybreon`
	`/* Minor optimisations (~10% faster)`
	`/*`
`/* Revision 1.1 2007/12/11 00:43:17 sybreon`	`/* Revision 1.1 2007/12/11 00:43:17 sybreon`
`/* initial import`	`/* initial import`
`/* */`	`/* */`
`No newline at end of file`	`No newline at end of file`

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/* $Id: aeMB2_bpcu.v,v 1.2 2007-12-12 19:16:59 sybreon Exp $

/* $Id: aeMB2_bpcu.v,v 1.3 2007-12-13 20:12:11 sybreon Exp $

**

**

** AEMB2 BRANCH/PROGRAMME COUNTER

** AEMB2 BRANCH/PROGRAMME COUNTER

**

**

** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>

** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>

**

**

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   // Outputs

   // Outputs

   iwb_adr_o, rPC_MA, rPC_IF, rIMM_IF, rALT_IF, rOPC_IF, rRD_IF,

   iwb_adr_o, rPC_MA, rPC_IF, rIMM_IF, rALT_IF, rOPC_IF, rRD_IF,

   rRA_IF, rRB_IF, rBRA,

   rRA_IF, rRB_IF, rBRA,

   // Inputs

   // Inputs

   iwb_dat_i, iwb_ack_i, rOPX_OF, rOPC_OF, rRA_OF, rRD_OF, rRES_EX,

   iwb_dat_i, iwb_ack_i, rOPX_OF, rOPC_OF, rRA_OF, rRD_OF, rRES_EX,

   rRD_EX, rOPD_EX, rMSR_TXE, clk_i, rst_i, ena_i, pha_i

   rRD_EX, rOPD_EX, clk_i, rst_i, ena_i, pha_i

);

);

   parameter IWB = 32;

   parameter IWB = 32;

   parameter TXE = 1;

   parameter TXE = 1;

   // IWB

   // IWB

Line 58...

   // MEMORY HAZARD DETECTION

   // MEMORY HAZARD DETECTION

   input [4:0]       rRD_EX; ///< RD

   input [4:0]       rRD_EX; ///< RD

   input [2:0]       rOPD_EX; ///< data register source (ALU, MEM/FSL, PC)

   input [2:0]       rOPD_EX; ///< data register source (ALU, MEM/FSL, PC)

   // SYSTEM

   // SYSTEM

   input            rMSR_TXE;

   input            clk_i,

   input            clk_i,

                    rst_i,

                    rst_i,

                    ena_i,

                    ena_i,

                    pha_i;

                    pha_i;

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   reg [31:2]           rPC, // PC

   reg [31:2]           rPC, // PC

                        rPC0, rPC1,// register based

                        rPC0, rPC1,// register based

                        rPCL[0:1]; // LUT based

                        rPCL[0:1]; // LUT based

   wire [31:2]          wPCNXT = (pha_i) ? rPC0 : (TXE) ? rPC1 : 30'hX;

   wire [31:2]          wPCNXT = (pha_i) ? rPC0 : rPC1;

   wire [31:2]          wPCINC = (rPC + 1);

   wire [31:2]          wPCINC = (rPC + 1);

   /* Check for RW data hazard */

   /* Check for RW data hazard */

   // TODO: Optimise

   // TODO: Optimise

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        /*AUTORESET*/

        /*AUTORESET*/

        // Beginning of autoreset for uninitialized flops

        // Beginning of autoreset for uninitialized flops

        rPC0 <= 30'h0;

        rPC0 <= 30'h0;

        rPC1 <= 30'h0;

        rPC1 <= 30'h0;

        // End of automatics

        // End of automatics

     end else begin

     end else if (ena_i) begin

        if (pha_i & ena_i & rMSR_TXE) rPC1 <= #1 wPCINC;

        if (pha_i)

        if (!pha_i & ena_i) rPC0 <= #1 wPCINC;

          rPC1 <= #1 wPCINC;

        else

          rPC0 <= #1 wPCINC;

end

end

/*

/*

    INSTRUCTION LATCH

    INSTRUCTION LATCH

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end

end

endmodule // aeMB2_bpcu

endmodule // aeMB2_bpcu

/* $Log: not supported by cvs2svn $

/* $Log: not supported by cvs2svn $

/* Revision 1.2  2007/12/12 19:16:59  sybreon

/* Minor optimisations (~10% faster)

/*

/* Revision 1.1  2007/12/11 00:43:17  sybreon

/* Revision 1.1  2007/12/11 00:43:17  sybreon

/* initial import

/* initial import

/* */

/* */

 No newline at end of file

 No newline at end of file

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