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/* $Id: aeMB2_bpcu.v,v 1.3 2007-12-13 20:12:11 sybreon Exp $
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/* $Id: aeMB2_bpcu.v,v 1.4 2007-12-17 12:53:43 sybreon Exp $
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**
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**
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** AEMB2 BRANCH/PROGRAMME COUNTER
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** AEMB2 BRANCH/PROGRAMME COUNTER
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**
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**
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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**
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**
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reg [31:2] rPC, // PC
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reg [31:2] rPC, // PC
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rPC0, rPC1,// register based
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rPC0, rPC1,// register based
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rPCL[0:1]; // LUT based
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rPCL[0:1]; // LUT based
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wire [31:2] wPCNXT = (pha_i) ? rPC0 : rPC1;
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wire [31:2] wPCNXT = (pha_i | !TXE) ? rPC0 : rPC1;
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wire [31:2] wPCINC = (rPC + 1);
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wire [31:2] wPCINC = (rPC + 1);
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/* Check for RW data hazard */
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/* Check for RW data hazard */
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// TODO: Optimise
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// TODO: Optimise
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end
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end
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endmodule // aeMB2_bpcu
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endmodule // aeMB2_bpcu
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/* $Log: not supported by cvs2svn $
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/* $Log: not supported by cvs2svn $
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/* Revision 1.3 2007/12/13 20:12:11 sybreon
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/* Code cleanup + minor speed regression.
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/*
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/* Revision 1.2 2007/12/12 19:16:59 sybreon
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/* Revision 1.2 2007/12/12 19:16:59 sybreon
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/* Minor optimisations (~10% faster)
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/* Minor optimisations (~10% faster)
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/*
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/*
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/* Revision 1.1 2007/12/11 00:43:17 sybreon
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/* Revision 1.1 2007/12/11 00:43:17 sybreon
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/* initial import
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/* initial import
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