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/* $Id: aeMB2_bpcu.v,v 1.4 2007-12-17 12:53:43 sybreon Exp $
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/* $Id: aeMB2_bpcu.v,v 1.5 2007-12-21 22:39:38 sybreon Exp $
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**
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**
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** AEMB2 BRANCH/PROGRAMME COUNTER
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** AEMB2 BRANCH/PROGRAMME COUNTER
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**
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**
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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**
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**
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wire fMULT = (rOPD_EX == 3'o3);
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wire fMULT = (rOPD_EX == 3'o3);
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wire fWRE = |rRD_EX;
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wire fWRE = |rRD_EX;
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wire fOPBHZD = (rRB_IF == rRD_EX) & (fLOAD | fMULT) & !fMOV & !rOPC_IF[3] & fWRE;
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wire fOPBHZD = (rRB_IF == rRD_EX) & (fLOAD | fMULT) & !fMOV & !rOPC_IF[3] & fWRE;
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wire fOPAHZD = (rRA_IF == rRD_EX) & (fLOAD | fMULT) & !fBRU & fWRE;
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wire fOPAHZD = (rRA_IF == rRD_EX) & (fLOAD | fMULT) & !fBRU & fWRE;
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wire fOPDHZD = (rRD_IF == rRD_EX) & (fLOAD | fMULT) & fSTR & fWRE;
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wire fOPDHZD = (rRD_IF == rRD_EX) & (fLOAD | fMULT) & fSTR & fWRE;
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wire fHZD = fOPBHZD | fOPAHZD | fOPDHZD;
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wire fHZD = (fOPBHZD | fOPAHZD | fOPDHZD) & !rBRA[1];
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/*
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/*
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IWB PC OUTPUT
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IWB PC OUTPUT
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This is part of the address generation stage. It pre-selects the
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This is part of the address generation stage. It pre-selects the
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end
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end
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endmodule // aeMB2_bpcu
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endmodule // aeMB2_bpcu
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/* $Log: not supported by cvs2svn $
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/* $Log: not supported by cvs2svn $
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/* Revision 1.4 2007/12/17 12:53:43 sybreon
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/* Made idle thread PC track main PC.
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/*
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/* Revision 1.3 2007/12/13 20:12:11 sybreon
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/* Revision 1.3 2007/12/13 20:12:11 sybreon
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/* Code cleanup + minor speed regression.
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/* Code cleanup + minor speed regression.
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/*
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/*
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/* Revision 1.2 2007/12/12 19:16:59 sybreon
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/* Revision 1.2 2007/12/12 19:16:59 sybreon
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/* Minor optimisations (~10% faster)
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/* Minor optimisations (~10% faster)
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