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/* $Id: aeMB2_edk32.v,v 1.4 2007-12-13 20:12:11 sybreon Exp $
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/* $Id: aeMB2_edk32.v,v 1.5 2007-12-13 21:25:41 sybreon Exp $
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**
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**
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** AEMB2 HI-PERFORMANCE CPU
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** AEMB2 HI-PERFORMANCE CPU
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**
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**
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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**
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**
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cwb_tga_o, cwb_stb_o, cwb_sel_o, cwb_dat_o, cwb_adr_o,
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cwb_tga_o, cwb_stb_o, cwb_sel_o, cwb_dat_o, cwb_adr_o,
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// Inputs
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// Inputs
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sys_rst_i, sys_int_i, sys_clk_i, iwb_dat_i, iwb_ack_i, dwb_dat_i,
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sys_rst_i, sys_int_i, sys_clk_i, iwb_dat_i, iwb_ack_i, dwb_dat_i,
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dwb_ack_i, cwb_dat_i, cwb_ack_i
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dwb_ack_i, cwb_dat_i, cwb_ack_i
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);
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);
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parameter IWB = 32; ///< instruction wishbone address space
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parameter IWB = 32; // instruction wishbone address space
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parameter DWB = 32; ///< data wishbone address space
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parameter DWB = 32; // data wishbone address space
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parameter TXE = 1; ///< thread execution extension
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parameter TXE = 1; // thread execution extension
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parameter MUL = 1; ///< enable hardware multiplier
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parameter MUL = 1; // enable multiply instruction
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parameter BSF = 1; ///< enable barrel shifter
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parameter BSF = 1; // enable barrel shift instructions
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parameter FSL = 1; ///< enable FSL bus
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parameter FSL = 1; // enable get/put instructions
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/*AUTOOUTPUT*/
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/*AUTOOUTPUT*/
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// Beginning of automatic outputs (from unused autoinst outputs)
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// Beginning of automatic outputs (from unused autoinst outputs)
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output [6:2] cwb_adr_o; // From aslu of aeMB2_aslu.v
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output [6:2] cwb_adr_o; // From aslu of aeMB2_aslu.v
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output [31:0] cwb_dat_o; // From regf of aeMB2_regf.v
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output [31:0] cwb_dat_o; // From regf of aeMB2_regf.v
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endcase // case (rBRA)
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endcase // case (rBRA)
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// WRITEBACK
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// WRITEBACK
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$write("\t|");
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$write("\t|");
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if (regf.fWRE) begin
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if (|rRD_MA) begin
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case (rOPD_MA)
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case (rOPD_MA)
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2'o2: begin
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2'o2: begin
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if (rSEL_MA != 4'h0) $writeh("R",rRD_MA,"=RAM(",regf.rREGD,")");
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if (rSEL_MA != 4'h0) $writeh("R",rRD_MA,"=RAM(",regf.rREGD,")");
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if (rSEL_MA == 4'h0) $writeh("R",rRD_MA,"=FSL(",regf.rREGD,")");
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if (rSEL_MA == 4'h0) $writeh("R",rRD_MA,"=FSL(",regf.rREGD,")");
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end
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end
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// synopsys translate_on
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// synopsys translate_on
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endmodule // aeMB2_edk32
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endmodule // aeMB2_edk32
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/* $Log: not supported by cvs2svn $
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/* $Log: not supported by cvs2svn $
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/* Revision 1.4 2007/12/13 20:12:11 sybreon
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/* Code cleanup + minor speed regression.
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/*
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/* Revision 1.3 2007/12/12 19:16:59 sybreon
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/* Revision 1.3 2007/12/12 19:16:59 sybreon
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/* Minor optimisations (~10% faster)
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/* Minor optimisations (~10% faster)
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/*
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/*
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/* Revision 1.2 2007/12/11 00:43:17 sybreon
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/* Revision 1.2 2007/12/11 00:43:17 sybreon
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/* initial import
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/* initial import
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