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/* $Id: aeMB2_edk32.v,v 1.5 2007-12-13 21:25:41 sybreon Exp $
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/* $Id: aeMB2_edk32.v,v 1.6 2007-12-16 03:25:22 sybreon Exp $
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**
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**
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** AEMB2 HI-PERFORMANCE CPU
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** AEMB2 HI-PERFORMANCE CPU
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**
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**
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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**
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**
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire clk_i; // From sysc of aeMB2_sysc.v
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wire clk_i; // From sysc of aeMB2_sysc.v
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wire ena_i; // From sysc of aeMB2_sysc.v
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wire ena_i; // From sysc of aeMB2_sysc.v
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wire pha_i; // From sysc of aeMB2_sysc.v
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wire pha_i; // From sysc of aeMB2_sysc.v
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wire [10:0] rALT_IF; // From bpcu of aeMB2_bpcu.v
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wire [10:0] rALT_IF; // From bpcu of aeMB2_bpcu.v
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wire [2:0] rALU_OF; // From idmx of aeMB2_idmx.v
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wire [2:0] rALU_OF; // From ofid of aeMB2_ofid.v
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wire [1:0] rBRA; // From bpcu of aeMB2_bpcu.v
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wire [1:0] rBRA; // From bpcu of aeMB2_bpcu.v
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wire [15:0] rIMM_IF; // From bpcu of aeMB2_bpcu.v
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wire [15:0] rIMM_IF; // From bpcu of aeMB2_bpcu.v
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wire [15:0] rIMM_OF; // From idmx of aeMB2_idmx.v
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wire [15:0] rIMM_OF; // From ofid of aeMB2_ofid.v
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wire rINT; // From sysc of aeMB2_sysc.v
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wire rINT; // From sysc of aeMB2_sysc.v
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wire rMSR_BE; // From aslu of aeMB2_aslu.v
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wire rMSR_BE; // From aslu of aeMB2_aslu.v
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wire rMSR_BIP; // From aslu of aeMB2_aslu.v
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wire rMSR_BIP; // From aslu of aeMB2_aslu.v
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wire rMSR_IE; // From aslu of aeMB2_aslu.v
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wire rMSR_IE; // From aslu of aeMB2_aslu.v
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wire [31:0] rMUL_MA; // From aslu of aeMB2_aslu.v
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wire [31:0] rMUL_MA; // From aslu of aeMB2_aslu.v
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wire [31:0] rOPA_OF; // From opmx of aeMB2_opmx.v
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wire [31:0] rOPA_OF; // From ofid of aeMB2_ofid.v
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wire [31:0] rOPB_OF; // From opmx of aeMB2_opmx.v
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wire [31:0] rOPB_OF; // From ofid of aeMB2_ofid.v
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wire [5:0] rOPC_IF; // From bpcu of aeMB2_bpcu.v
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wire [5:0] rOPC_IF; // From bpcu of aeMB2_bpcu.v
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wire [5:0] rOPC_OF; // From idmx of aeMB2_idmx.v
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wire [5:0] rOPC_OF; // From ofid of aeMB2_ofid.v
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wire [2:0] rOPD_EX; // From idmx of aeMB2_idmx.v
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wire [2:0] rOPD_EX; // From ofid of aeMB2_ofid.v
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wire [2:0] rOPD_MA; // From idmx of aeMB2_idmx.v
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wire [2:0] rOPD_MA; // From ofid of aeMB2_ofid.v
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wire [31:0] rOPM_OF; // From opmx of aeMB2_opmx.v
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wire [31:0] rOPM_OF; // From ofid of aeMB2_ofid.v
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wire [31:0] rOPX_OF; // From opmx of aeMB2_opmx.v
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wire [31:0] rOPX_OF; // From ofid of aeMB2_ofid.v
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wire [31:2] rPC_IF; // From bpcu of aeMB2_bpcu.v
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wire [31:2] rPC_IF; // From bpcu of aeMB2_bpcu.v
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wire [31:2] rPC_MA; // From bpcu of aeMB2_bpcu.v
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wire [31:2] rPC_MA; // From bpcu of aeMB2_bpcu.v
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wire [4:0] rRA_IF; // From bpcu of aeMB2_bpcu.v
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wire [4:0] rRA_IF; // From bpcu of aeMB2_bpcu.v
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wire [4:0] rRA_OF; // From idmx of aeMB2_idmx.v
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wire [4:0] rRA_OF; // From ofid of aeMB2_ofid.v
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wire [4:0] rRB_IF; // From bpcu of aeMB2_bpcu.v
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wire [4:0] rRB_IF; // From bpcu of aeMB2_bpcu.v
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wire [4:0] rRD_EX; // From idmx of aeMB2_idmx.v
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wire [4:0] rRD_EX; // From ofid of aeMB2_ofid.v
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wire [4:0] rRD_IF; // From bpcu of aeMB2_bpcu.v
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wire [4:0] rRD_IF; // From bpcu of aeMB2_bpcu.v
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wire [4:0] rRD_MA; // From idmx of aeMB2_idmx.v
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wire [4:0] rRD_MA; // From ofid of aeMB2_ofid.v
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wire [4:0] rRD_OF; // From idmx of aeMB2_idmx.v
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wire [4:0] rRD_OF; // From ofid of aeMB2_ofid.v
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wire [31:0] rREGA_OF; // From regf of aeMB2_regf.v
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wire [31:0] rREGA_OF; // From regf of aeMB2_regf.v
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wire [31:0] rREGB_OF; // From regf of aeMB2_regf.v
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wire [31:0] rREGB_OF; // From regf of aeMB2_regf.v
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wire [31:0] rREGD_OF; // From regf of aeMB2_regf.v
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wire [31:0] rREGD_OF; // From regf of aeMB2_regf.v
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wire [31:0] rRES_EX; // From aslu of aeMB2_aslu.v
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wire [31:0] rRES_EX; // From aslu of aeMB2_aslu.v
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wire [31:0] rRES_MA; // From aslu of aeMB2_aslu.v
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wire [31:0] rRES_MA; // From aslu of aeMB2_aslu.v
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Line 226... |
.ena_i (ena_i),
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.ena_i (ena_i),
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.pha_i (pha_i));
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.pha_i (pha_i));
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/* Operand Fetch Mux */
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/* Operand Fetch Mux */
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aeMB2_opmx
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aeMB2_ofid
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#(/*AUTOINSTPARAM*/
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// Parameters
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.TXE (TXE))
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opmx (/*AUTOINST*/
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// Outputs
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.rOPM_OF (rOPM_OF[31:0]),
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.rOPX_OF (rOPX_OF[31:0]),
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.rOPA_OF (rOPA_OF[31:0]),
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.rOPB_OF (rOPB_OF[31:0]),
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// Inputs
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.rRES_EX (rRES_EX[31:0]),
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.rRD_EX (rRD_EX[4:0]),
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.rOPD_EX (rOPD_EX[1:0]),
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.rOPC_IF (rOPC_IF[5:0]),
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.rIMM_IF (rIMM_IF[15:0]),
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.rPC_IF (rPC_IF[31:2]),
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.rRD_IF (rRD_IF[4:0]),
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.rRA_IF (rRA_IF[4:0]),
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.rRB_IF (rRB_IF[4:0]),
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.rREGD_OF (rREGD_OF[31:0]),
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.rREGA_OF (rREGA_OF[31:0]),
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.rREGB_OF (rREGB_OF[31:0]),
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.rBRA (rBRA[1:0]),
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.pha_i (pha_i),
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.clk_i (clk_i),
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.rst_i (rst_i),
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.ena_i (ena_i));
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/* Instruction Decode Mux */
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aeMB2_idmx
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#(/*AUTOINSTPARAM*/
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#(/*AUTOINSTPARAM*/
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// Parameters
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// Parameters
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.TXE (TXE),
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.TXE (TXE),
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.MUL (MUL),
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.MUL (MUL),
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.BSF (BSF),
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.BSF (BSF),
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.FSL (FSL))
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.FSL (FSL))
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idmx (/*AUTOINST*/
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ofid (/*AUTOINST*/
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// Outputs
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// Outputs
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.rOPM_OF (rOPM_OF[31:0]),
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.rOPX_OF (rOPX_OF[31:0]),
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.rOPA_OF (rOPA_OF[31:0]),
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.rOPB_OF (rOPB_OF[31:0]),
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.rIMM_OF (rIMM_OF[15:0]),
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.rIMM_OF (rIMM_OF[15:0]),
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.rOPC_OF (rOPC_OF[5:0]),
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.rOPC_OF (rOPC_OF[5:0]),
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.rRA_OF (rRA_OF[4:0]),
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.rRA_OF (rRA_OF[4:0]),
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.rRD_OF (rRD_OF[4:0]),
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.rRD_OF (rRD_OF[4:0]),
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.rRD_EX (rRD_EX[4:0]),
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.rRD_EX (rRD_EX[4:0]),
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.rRD_MA (rRD_MA[4:0]),
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.rRD_MA (rRD_MA[4:0]),
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.rOPD_EX (rOPD_EX[2:0]),
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.rOPD_EX (rOPD_EX[2:0]),
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.rOPD_MA (rOPD_MA[2:0]),
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.rOPD_MA (rOPD_MA[2:0]),
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.rALU_OF (rALU_OF[2:0]),
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.rALU_OF (rALU_OF[2:0]),
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// Inputs
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// Inputs
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.rRES_EX (rRES_EX[31:0]),
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.rREGD_OF (rREGD_OF[31:0]),
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.rREGA_OF (rREGA_OF[31:0]),
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.rREGB_OF (rREGB_OF[31:0]),
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.rBRA (rBRA[1:0]),
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.rBRA (rBRA[1:0]),
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.rXCE (rXCE),
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.rXCE (rXCE),
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.rINT (rINT),
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.rINT (rINT),
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.rPC_IF (rPC_IF[31:2]),
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.rIMM_IF (rIMM_IF[15:0]),
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.rIMM_IF (rIMM_IF[15:0]),
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.rALT_IF (rALT_IF[10:0]),
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.rALT_IF (rALT_IF[10:0]),
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.rOPC_IF (rOPC_IF[5:0]),
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.rOPC_IF (rOPC_IF[5:0]),
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.rRA_IF (rRA_IF[4:0]),
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.rRA_IF (rRA_IF[4:0]),
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.rRB_IF (rRB_IF[4:0]),
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.rRB_IF (rRB_IF[4:0]),
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Line 324... |
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$writeh ("\t| ");
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$writeh ("\t| ");
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case (rOPC_IF)
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case (rOPC_IF)
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6'o00: if (rRD_IF == 0) $write(" "); else $write("ADD");
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6'o00: if (rRD_IF == 0) $write(" "); else $write("ADD");
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6'o01: $write("RSUB");
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6'o01: $write("SUB");
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6'o02: $write("ADDC");
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6'o02: $write("ADDC");
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6'o03: $write("RSUBC");
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6'o03: $write("SUBC");
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6'o04: $write("ADDK");
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6'o04: $write("ADDK");
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6'o05: case (rIMM_IF[1:0])
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6'o05: case (rIMM_IF[1:0])
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2'o0: $write("RSUBK");
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2'o0: $write("SUBK");
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2'o1: $write("CMP");
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2'o1: $write("CMP");
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2'o3: $write("CMPU");
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2'o3: $write("CMPU");
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default: $write("XXX");
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default: $write("XXX");
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endcase // case (rIMM_IF[1:0])
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endcase // case (rIMM_IF[1:0])
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6'o06: $write("ADDKC");
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6'o06: $write("ADDKC");
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6'o07: $write("RSUBKC");
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6'o07: $write("SUBKC");
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6'o10: $write("ADDI");
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6'o10: $write("ADDI");
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6'o11: $write("RSUBI");
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6'o11: $write("SUBI");
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6'o12: $write("ADDIC");
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6'o12: $write("ADDIC");
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6'o13: $write("RSUBIC");
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6'o13: $write("SUBIC");
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6'o14: $write("ADDIK");
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6'o14: $write("ADDIK");
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6'o15: $write("RSUBIK");
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6'o15: $write("SUBIK");
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6'o16: $write("ADDIKC");
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6'o16: $write("ADDIKC");
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6'o17: $write("RSUBIKC");
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6'o17: $write("SUBIKC");
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6'o20: $write("MUL");
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6'o20: $write("MUL");
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6'o21: case (rALT_IF[10:9])
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6'o21: case (rALT_IF[10:9])
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2'o0: $write("BSRL");
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2'o0: $write("BSRL");
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2'o1: $write("BSRA");
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2'o1: $write("BSRA");
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| Line 546... |
Line 524... |
// synopsys translate_on
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// synopsys translate_on
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endmodule // aeMB2_edk32
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endmodule // aeMB2_edk32
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/* $Log: not supported by cvs2svn $
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/* $Log: not supported by cvs2svn $
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/* Revision 1.5 2007/12/13 21:25:41 sybreon
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/* Further optimisations (speed + size).
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/*
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/* Revision 1.4 2007/12/13 20:12:11 sybreon
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/* Revision 1.4 2007/12/13 20:12:11 sybreon
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/* Code cleanup + minor speed regression.
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/* Code cleanup + minor speed regression.
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/*
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/*
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/* Revision 1.3 2007/12/12 19:16:59 sybreon
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/* Revision 1.3 2007/12/12 19:16:59 sybreon
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/* Minor optimisations (~10% faster)
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/* Minor optimisations (~10% faster)
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