OpenCores

Rev 80	Rev 81
Line 1...	Line 1...
`/* $Id: aeMB2_idmx.v,v 1.2 2007-12-12 19:16:59 sybreon Exp $`	`/* $Id: aeMB2_idmx.v,v 1.3 2007-12-13 20:12:11 sybreon Exp $`
`**`	`**`
`** AEMB2 INSTRUCTION DECODE MUX`	`** AEMB2 INSTRUCTION DECODE MUX`
`**`	`**`
`** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>`	`** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>`
`**`	`**`
Line 24...	Line 24...
`// Outputs`	`// Outputs`
`rIMM_OF, rOPC_OF, rRA_OF, rRD_OF, rRD_EX, rRD_MA, rOPD_EX, rOPD_MA,`	`rIMM_OF, rOPC_OF, rRA_OF, rRD_OF, rRD_EX, rRD_MA, rOPD_EX, rOPD_MA,`
`rALU_OF,`	`rALU_OF,`
`// Inputs`	`// Inputs`
`rBRA, rXCE, rINT, rIMM_IF, rALT_IF, rOPC_IF, rRA_IF, rRB_IF,`	`rBRA, rXCE, rINT, rIMM_IF, rALT_IF, rOPC_IF, rRA_IF, rRB_IF,`
`rRD_IF, rMSR_TXE, pha_i, clk_i, rst_i, ena_i`	`rRD_IF, pha_i, clk_i, rst_i, ena_i`
`);`	`);`
`parameter TXE = 1;`	`parameter TXE = 1;`

`parameter MUL = 1;`	`parameter MUL = 1;`
`parameter BSF = 1;`	`parameter BSF = 1;`
Line 47...	Line 47...
`output [2:0] rALU_OF; // addsub, logic, bshift, sext, mul, mov, ldst`	`output [2:0] rALU_OF; // addsub, logic, bshift, sext, mul, mov, ldst`


`input [1:0] rBRA;`	`input [1:0] rBRA;`
`input rXCE,`	`input rXCE,`
	`//rMSR_TXE,`
`rINT;`	`rINT;`

`input [15:0] rIMM_IF;`	`input [15:0] rIMM_IF;`
`input [10:0] rALT_IF;`	`input [10:0] rALT_IF;`
`input [5:0] rOPC_IF;`	`input [5:0] rOPC_IF;`
`input [4:0] rRA_IF,`	`input [4:0] rRA_IF,`
`rRB_IF,`	`rRB_IF,`
`rRD_IF;`	`rRD_IF;`

`input rMSR_TXE;`

`input pha_i,`	`input pha_i,`
`clk_i,`	`clk_i,`
`rst_i,`	`rst_i,`
`ena_i;`	`ena_i;`

Line 112...	Line 111...
`wire fOPAHZD = (rRA_IF == rRD_EX) & (fLOAD \| fMULT) & !fBRU & fWRE;`	`wire fOPAHZD = (rRA_IF == rRD_EX) & (fLOAD \| fMULT) & !fBRU & fWRE;`
`wire fOPDHZD = (rRD_IF == rRD_EX) & (fLOAD \| fMULT) & fSTR & fWRE;`	`wire fOPDHZD = (rRD_IF == rRD_EX) & (fLOAD \| fMULT) & fSTR & fWRE;`
`wire fHAZARD = fOPBHZD \| fOPAHZD \| fOPDHZD;`	`wire fHAZARD = fOPBHZD \| fOPAHZD \| fOPDHZD;`

`wire fSKIP = (rBRA == 2'o2) \| // non-delay branch`	`wire fSKIP = (rBRA == 2'o2) \| // non-delay branch`
`!(rMSR_TXE \| pha_i) \|`	`!(TXE \| pha_i) \|`
`fOPBHZD \| fOPAHZD; // hazards`	`fOPBHZD \| fOPAHZD; // hazards`

`/* ALU Selector */`	`/* ALU Selector */`

`always @(posedge clk_i)`	`always @(posedge clk_i)`
Line 188...	Line 187...
`end // if (ena_i)`	`end // if (ena_i)`

`endmodule // aeMB2_idmx`	`endmodule // aeMB2_idmx`

`/* $Log: not supported by cvs2svn $`	`/* $Log: not supported by cvs2svn $`
	`/* Revision 1.2 2007/12/12 19:16:59 sybreon`
	`/* Minor optimisations (~10% faster)`
	`/*`
`/* Revision 1.1 2007/12/11 00:43:17 sybreon`	`/* Revision 1.1 2007/12/11 00:43:17 sybreon`
`/* initial import`	`/* initial import`
`/* */`	`/* */`
`No newline at end of file`	`No newline at end of file`

Line 1...

/* $Id: aeMB2_idmx.v,v 1.2 2007-12-12 19:16:59 sybreon Exp $

/* $Id: aeMB2_idmx.v,v 1.3 2007-12-13 20:12:11 sybreon Exp $

**

**

** AEMB2 INSTRUCTION DECODE MUX

** AEMB2 INSTRUCTION DECODE MUX

**

**

** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>

** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>

**

**

Line 24...

   // Outputs

   // Outputs

   rIMM_OF, rOPC_OF, rRA_OF, rRD_OF, rRD_EX, rRD_MA, rOPD_EX, rOPD_MA,

   rIMM_OF, rOPC_OF, rRA_OF, rRD_OF, rRD_EX, rRD_MA, rOPD_EX, rOPD_MA,

   rALU_OF,

   rALU_OF,

   // Inputs

   // Inputs

   rBRA, rXCE, rINT, rIMM_IF, rALT_IF, rOPC_IF, rRA_IF, rRB_IF,

   rBRA, rXCE, rINT, rIMM_IF, rALT_IF, rOPC_IF, rRA_IF, rRB_IF,

   rRD_IF, rMSR_TXE, pha_i, clk_i, rst_i, ena_i

   rRD_IF, pha_i, clk_i, rst_i, ena_i

);

);

   parameter TXE = 1;

   parameter TXE = 1;

   parameter MUL = 1;

   parameter MUL = 1;

   parameter BSF = 1;

   parameter BSF = 1;

Line 47...

   output [2:0]  rALU_OF; // addsub, logic, bshift, sext, mul, mov, ldst

   output [2:0]  rALU_OF; // addsub, logic, bshift, sext, mul, mov, ldst

   input [1:0]    rBRA;

   input [1:0]    rBRA;

   input         rXCE,

   input         rXCE,

                 //rMSR_TXE,

                 rINT;

                 rINT;

   input [15:0]  rIMM_IF;

   input [15:0]  rIMM_IF;

   input [10:0]  rALT_IF;

   input [10:0]  rALT_IF;

   input [5:0]    rOPC_IF;

   input [5:0]    rOPC_IF;

   input [4:0]    rRA_IF,

   input [4:0]    rRA_IF,

                 rRB_IF,

                 rRB_IF,

                 rRD_IF;

                 rRD_IF;

   input         rMSR_TXE;

   input         pha_i,

   input         pha_i,

                 clk_i,

                 clk_i,

                 rst_i,

                 rst_i,

                 ena_i;

                 ena_i;

Line 112...

Line 111...

   wire                 fOPAHZD = (rRA_IF == rRD_EX) & (fLOAD | fMULT) & !fBRU & fWRE;

   wire                 fOPAHZD = (rRA_IF == rRD_EX) & (fLOAD | fMULT) & !fBRU & fWRE;

   wire                 fOPDHZD = (rRD_IF == rRD_EX) & (fLOAD | fMULT) & fSTR & fWRE;

   wire                 fOPDHZD = (rRD_IF == rRD_EX) & (fLOAD | fMULT) & fSTR & fWRE;

   wire                 fHAZARD = fOPBHZD | fOPAHZD | fOPDHZD;

   wire                 fHAZARD = fOPBHZD | fOPAHZD | fOPDHZD;

   wire                 fSKIP = (rBRA == 2'o2) | // non-delay branch

   wire                 fSKIP = (rBRA == 2'o2) | // non-delay branch

                        !(rMSR_TXE | pha_i) |

                        !(TXE | pha_i) |

                        fOPBHZD | fOPAHZD; // hazards

                        fOPBHZD | fOPAHZD; // hazards

   /* ALU Selector */

   /* ALU Selector */

   always @(posedge clk_i)

   always @(posedge clk_i)

Line 188...

Line 187...

     end // if (ena_i)

     end // if (ena_i)

endmodule // aeMB2_idmx

endmodule // aeMB2_idmx

/* $Log: not supported by cvs2svn $

/* $Log: not supported by cvs2svn $

/* Revision 1.2  2007/12/12 19:16:59  sybreon

/* Minor optimisations (~10% faster)

/*

/* Revision 1.1  2007/12/11 00:43:17  sybreon

/* Revision 1.1  2007/12/11 00:43:17  sybreon

/* initial import

/* initial import

/* */

/* */

 No newline at end of file

 No newline at end of file

Browse

Tools

Subversion Repositories aemb

[/] [aemb/] [branches/] [DEV_SYBREON/] [rtl/] [verilog/] [aeMB2_idmx.v] - Diff between revs 80 and 81