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/* $Id: aeMB2_idmx.v,v 1.4 2007-12-13 21:25:41 sybreon Exp $
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/* $Id: aeMB2_idmx.v,v 1.5 2007-12-16 03:25:02 sybreon Exp $
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**
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**
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** AEMB2 INSTRUCTION DECODE MUX
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** AEMB2 INSTRUCTION DECODE MUX
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**
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**
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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**
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**
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wire fSKIP = (rBRA == 2'o2) | // non-delay branch
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wire fSKIP = (rBRA == 2'o2) | // non-delay branch
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!(TXE | pha_i) |
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!(TXE | pha_i) |
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fOPBHZD | fOPAHZD; // hazards
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fOPBHZD | fOPAHZD; // hazards
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/*
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PARTIAL IMMI
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Replicated from OPMX and used for checking atomicity for
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interrupts. */
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reg rFIM0, rFIM1, rFIML[0:1];
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wire rFIM = (pha_i) ? rFIM0 : rFIM1;
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wire fSKP = rBRA == 2'b10;
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wire fINT = !rFIM & !rBRA[1] & rINT & pha_i;
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always @(posedge clk_i)
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if (rst_i) begin
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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rFIM0 <= 1'h0;
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rFIM1 <= 1'h0;
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// End of automatics
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end else if (ena_i) begin
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if (pha_i)
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rFIM0 <= #1 fIMM & !fSKP;
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else
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rFIM1 <= #1 fIMM & !fSKP;
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end
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/* ALU Selector */
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/* ALU Selector */
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always @(posedge clk_i)
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always @(posedge clk_i)
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if (rst_i) begin
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if (rst_i) begin
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/*AUTORESET*/
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/*AUTORESET*/
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(fMUL) ? 3'o4 :
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(fMUL) ? 3'o4 :
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(fBSF) ? 3'o5 :
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(fBSF) ? 3'o5 :
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3'o0;
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3'o0;
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*/
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*/
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rALU_OF <= #1
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rALU_OF <= #1
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(fSKIP) ? 3'o1 : // NOP
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(fSKIP) ? 3'o2 : // NOP
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(fBRA | fMOV) ? 3'o1 :
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(fBRA | fMOV) ? 3'o2 :
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(fSFT) ? 3'o1 :
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(fSFT) ? 3'o2 :
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(fLOG) ? 3'o1 :
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(fLOG) ? 3'o2 :
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(fBSF) ? 3'o2 :
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(fBSF) ? 3'o1 :
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3'o0;
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3'o0;
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end
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end // if (ena_i)
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/* WB Selector */
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/* WB Selector */
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reg [2:0] rOPD_OF;
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reg [2:0] rOPD_OF;
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(fMUL) ? 3'o3 : // MUL
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(fMUL) ? 3'o3 : // MUL
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(|rRD_IF) ? 3'o0 : // ALU
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(|rRD_IF) ? 3'o0 : // ALU
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3'o7; // NOP
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3'o7; // NOP
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end // if (ena_i)
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end // if (ena_i)
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/* Passthrough */
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// The only non atomic instruction is IMMI. All other instructions
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// are atomic. No interception allowed for branching.
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/*
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INTERCEPTION
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Instructions are either pass-thru or intercepted here. */
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always @(posedge clk_i)
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always @(posedge clk_i)
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if (rst_i) begin
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if (rst_i) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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end else if (ena_i) begin // if (rst_i)
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end else if (ena_i) begin // if (rst_i)
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rRD_MA <= #1 rRD_EX;
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rRD_MA <= #1 rRD_EX;
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rRD_EX <= #1 rRD_OF;
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rRD_EX <= #1 rRD_OF;
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// TODO: Interrrupt
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// TODO: Interrrupt
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case (fSKIP)
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case ({fINT, fSKIP})
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2'o0: {rOPC_OF, rRD_OF, rRA_OF, rIMM_OF} <= #1 {rOPC_IF, rRD_IF, rRA_IF, rIMM_IF};
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2'o0: {rOPC_OF, rRD_OF, rRA_OF, rIMM_OF} <= #1 {rOPC_IF, rRD_IF, rRA_IF, rIMM_IF};
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2'o1: {rOPC_OF, rRD_OF, rRA_OF, rIMM_OF} <= #1 wNOPOP; // delay/stall
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2'o1: {rOPC_OF, rRD_OF, rRA_OF, rIMM_OF} <= #1 wNOPOP; // delay/stall
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2'o3,
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2'o2: {rOPC_OF, rRD_OF, rRA_OF, rIMM_OF} <= #1 wINTOP; // interrupt
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default: {rOPC_OF, rRD_OF, rRA_OF} <= #1 16'hX;
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default: {rOPC_OF, rRD_OF, rRA_OF} <= #1 16'hX;
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endcase // case (fSKIP)
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endcase // case (fSKIP)
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end // if (ena_i)
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end // if (ena_i)
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endmodule // aeMB2_idmx
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endmodule // aeMB2_idmx
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/* $Log: not supported by cvs2svn $
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/* $Log: not supported by cvs2svn $
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/* Revision 1.4 2007/12/13 21:25:41 sybreon
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/* Further optimisations (speed + size).
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/*
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/* Revision 1.3 2007/12/13 20:12:11 sybreon
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/* Revision 1.3 2007/12/13 20:12:11 sybreon
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/* Code cleanup + minor speed regression.
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/* Code cleanup + minor speed regression.
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/*
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/*
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/* Revision 1.2 2007/12/12 19:16:59 sybreon
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/* Revision 1.2 2007/12/12 19:16:59 sybreon
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/* Minor optimisations (~10% faster)
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/* Minor optimisations (~10% faster)
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