| Line 1... |
Line 1... |
/* $Id: aeMB2_sysc.v,v 1.2 2007-12-12 19:16:59 sybreon Exp $
|
/* $Id: aeMB2_sysc.v,v 1.3 2007-12-13 20:12:11 sybreon Exp $
|
**
|
**
|
** AEMB2 SYSTEM CONTROL
|
** AEMB2 SYSTEM CONTROL
|
**
|
**
|
** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
|
** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
|
**
|
**
|
| Line 20... |
Line 20... |
** License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
|
** License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
|
*/
|
*/
|
|
|
module aeMB2_sysc (/*AUTOARG*/
|
module aeMB2_sysc (/*AUTOARG*/
|
// Outputs
|
// Outputs
|
iwb_stb_o, iwb_wre_o, dwb_cyc_o, dwb_stb_o, dwb_wre_o, cwb_stb_o,
|
rINT, rXCE, pha_o, clk_o, rst_o, ena_o, iwb_stb_o, iwb_wre_o,
|
cwb_wre_o, rINT, rXCE, pha_o, clk_o, rst_o, ena_o,
|
dwb_cyc_o, dwb_stb_o, dwb_wre_o, cwb_stb_o, cwb_wre_o,
|
// Inputs
|
// Inputs
|
rOPC_IF, iwb_ack_i, dwb_ack_i, cwb_ack_i, rIMM_OF, rOPC_OF, rRA_OF,
|
rIMM_OF, rOPC_OF, rRA_OF, rMSR_BE, rMSR_BIP, rMSR_IE, rOPC_IF,
|
rMSR_TXE, rMSR_BE, rMSR_BIP, rMSR_IE, sys_int_i, sys_clk_i,
|
iwb_ack_i, dwb_ack_i, cwb_ack_i, sys_int_i, sys_clk_i, sys_rst_i
|
sys_rst_i
|
|
);
|
);
|
parameter TXE = 1;
|
parameter TXE = 1;
|
parameter FSL = 1;
|
parameter FSL = 1;
|
|
|
// INTERNAL
|
// INTERNAL
|
|
input [15:0] rIMM_OF;
|
|
input [5:0] rOPC_OF;
|
|
input [4:0] rRA_OF;
|
|
input rMSR_BE,
|
|
rMSR_BIP,
|
|
//rMSR_TXE,
|
|
rMSR_IE;
|
input [5:0] rOPC_IF;
|
input [5:0] rOPC_IF;
|
|
|
|
output rINT,
|
|
rXCE;
|
|
|
|
output pha_o,
|
|
clk_o,
|
|
rst_o,
|
|
ena_o;
|
|
|
// EXTERNAL
|
// EXTERNAL
|
output iwb_stb_o,
|
output iwb_stb_o,
|
iwb_wre_o,
|
iwb_wre_o,
|
dwb_cyc_o,
|
dwb_cyc_o,
|
| Line 47... |
Line 60... |
|
|
input iwb_ack_i,
|
input iwb_ack_i,
|
dwb_ack_i,
|
dwb_ack_i,
|
cwb_ack_i;
|
cwb_ack_i;
|
|
|
// INTERNAL
|
|
output rINT,
|
|
rXCE;
|
|
input [15:0] rIMM_OF;
|
|
input [5:0] rOPC_OF;
|
|
input [4:0] rRA_OF;
|
|
input rMSR_TXE,
|
|
rMSR_BE,
|
|
rMSR_BIP,
|
|
rMSR_IE;
|
|
|
|
output pha_o,
|
|
clk_o,
|
|
rst_o,
|
|
ena_o;
|
|
|
|
// SYSTEM
|
// SYSTEM
|
input sys_int_i,
|
input sys_int_i,
|
sys_clk_i,
|
sys_clk_i,
|
sys_rst_i;
|
sys_rst_i;
|
|
|
| Line 140... |
Line 137... |
end
|
end
|
|
|
/* Level triggered interrupt latch flag */
|
/* Level triggered interrupt latch flag */
|
|
|
// check for interrupt acknowledge
|
// check for interrupt acknowledge
|
wire fINTACK = ena_o & (rOPC_OF == 6'o56) & (rRA_OF == 5'h0D);
|
wire fINTACK = ena_o & (rOPC_OF == 6'o56) & (rRA_OF == 5'h0E);
|
|
|
always @(posedge clk_o)
|
always @(posedge clk_o)
|
if (rst_o) begin
|
if (rst_o) begin
|
/*AUTORESET*/
|
/*AUTORESET*/
|
// Beginning of autoreset for uninitialized flops
|
// Beginning of autoreset for uninitialized flops
|
| Line 167... |
Line 164... |
(rOPC_OF[2]))) | // GET/PUT
|
(rOPC_OF[2]))) | // GET/PUT
|
((rOPC_IF[5:3] == 3'o2) &
|
((rOPC_IF[5:3] == 3'o2) &
|
(rOPC_IF[2:1] != 2'o0)) // MUL/BSF
|
(rOPC_IF[2:1] != 2'o0)) // MUL/BSF
|
;
|
;
|
|
|
always @(posedge clk_o)
|
|
if (rst_o) begin
|
|
/*AUTORESET*/
|
|
// Beginning of autoreset for uninitialized flops
|
|
rINT <= 1'h0;
|
|
// End of automatics
|
|
end else if (rMSR_IE) begin
|
|
rINT <= #1 rINT | sys_int_i & !fINTACK;
|
|
end
|
|
|
|
/* Handle wishbone handshakes */
|
/* Handle wishbone handshakes */
|
|
|
assign iwb_wre_o = 1'b0;
|
assign iwb_wre_o = 1'b0;
|
|
|
always @(posedge clk_o)
|
always @(posedge clk_o)
|
| Line 193... |
Line 180... |
dwb_stb_o <= 1'h0;
|
dwb_stb_o <= 1'h0;
|
dwb_wre_o <= 1'h0;
|
dwb_wre_o <= 1'h0;
|
iwb_stb_o <= 1'h0;
|
iwb_stb_o <= 1'h0;
|
// End of automatics
|
// End of automatics
|
end else begin
|
end else begin
|
iwb_stb_o <= #1 (rMSR_TXE | pha_o);
|
iwb_stb_o <= #1 (TXE | pha_o);
|
|
|
dwb_cyc_o <= #1 fLOD | fSTR | rMSR_BE;
|
dwb_cyc_o <= #1 fLOD | fSTR | rMSR_BE;
|
dwb_stb_o <= #1 fLOD | fSTR;
|
dwb_stb_o <= #1 fLOD | fSTR;
|
dwb_wre_o <= #1 fSTR;
|
dwb_wre_o <= #1 fSTR;
|
|
|
cwb_stb_o <= #1 (FSL) ? fGET | fPUT : 1'bX;
|
cwb_stb_o <= #1 (FSL) ? (fGET | fPUT) : 1'bX;
|
cwb_wre_o <= #1 (FSL) ? fPUT : 1'bX;
|
cwb_wre_o <= #1 (FSL) ? fPUT : 1'bX;
|
end
|
end
|
|
|
|
|
|
|
endmodule // aeMB2_sysc
|
endmodule // aeMB2_sysc
|
|
|
/* $Log: not supported by cvs2svn $
|
/* $Log: not supported by cvs2svn $
|
|
/* Revision 1.2 2007/12/12 19:16:59 sybreon
|
|
/* Minor optimisations (~10% faster)
|
|
/*
|
/* Revision 1.1 2007/12/11 00:43:17 sybreon
|
/* Revision 1.1 2007/12/11 00:43:17 sybreon
|
/* initial import
|
/* initial import
|
/* */
|
/* */
|
No newline at end of file
|
No newline at end of file
|
