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[/] [aemb/] [branches/] [DEV_SYBREON/] [rtl/] [verilog/] [aeMB2_sysc.v] - Diff between revs 84 and 93

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/* $Id: aeMB2_sysc.v,v 1.4 2007-12-16 03:25:02 sybreon Exp $
/* $Id: aeMB2_sysc.v,v 1.5 2007-12-21 22:28:56 sybreon Exp $
**
**
** AEMB2 SYSTEM CONTROL
** AEMB2 SYSTEM CONTROL
**
**
** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
**
**
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        dwb_cyc_o <= 1'h0;
        dwb_cyc_o <= 1'h0;
        dwb_stb_o <= 1'h0;
        dwb_stb_o <= 1'h0;
        dwb_wre_o <= 1'h0;
        dwb_wre_o <= 1'h0;
        iwb_stb_o <= 1'h0;
        iwb_stb_o <= 1'h0;
        // End of automatics
        // End of automatics
     end else begin
     end else if (ena_o) begin
        iwb_stb_o <= #1 (TXE | pha_o);
        iwb_stb_o <= #1 (TXE | pha_o);
 
 
        dwb_cyc_o <= #1 fLOD | fSTR | rMSR_BE;
        dwb_cyc_o <= #1 fLOD | fSTR | rMSR_BE;
        dwb_stb_o <= #1 fLOD | fSTR;
        dwb_stb_o <= #1 fLOD | fSTR;
        dwb_wre_o <= #1 fSTR;
        dwb_wre_o <= #1 fSTR;
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endmodule // aeMB2_sysc
endmodule // aeMB2_sysc
 
 
/* $Log: not supported by cvs2svn $
/* $Log: not supported by cvs2svn $
 
/* Revision 1.4  2007/12/16 03:25:02  sybreon
 
/* Added interrupt support.
 
/*
/* Revision 1.3  2007/12/13 20:12:11  sybreon
/* Revision 1.3  2007/12/13 20:12:11  sybreon
/* Code cleanup + minor speed regression.
/* Code cleanup + minor speed regression.
/*
/*
/* Revision 1.2  2007/12/12 19:16:59  sybreon
/* Revision 1.2  2007/12/12 19:16:59  sybreon
/* Minor optimisations (~10% faster)
/* Minor optimisations (~10% faster)

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