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// -*- Mode: Verilog -*-
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// -*- Mode: Verilog -*-
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// Filename : aeMB_core.v
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// Filename : aeMB_core.v
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// Description : Microblaze Compatible Core
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// Description : Microblaze Compatible Core
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// Author : Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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// Author : Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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// Created On : Fri Dec 29 16:15:18 2006
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// Created On : Fri Dec 29 16:15:18 2006
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// Last Modified By: Shawn Tan
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// Last Modified By: $Author: sybreon $
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// Last Modified On: 2006-12-29
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// Last Modified On: $Date: 2007-04-04 06:13:23 $
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// Update Count : 0
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// Update Count : $Revision: 1.2 $
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// Status : Unknown, Use with caution!
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// Status : $State: Exp $
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/*
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/*
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* $Id: aeMB_core.v,v 1.1 2007-03-09 17:52:17 sybreon Exp $
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* $Id: aeMB_core.v,v 1.2 2007-04-04 06:13:23 sybreon Exp $
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*
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*
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* AEMB 32-bit Microblaze Compatible Core
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* Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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* Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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*
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*
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* This library is free software; you can redistribute it and/or modify it
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* This library is free software; you can redistribute it and/or modify it
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* under the terms of the GNU Lesser General Public License as published by
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* under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation; either version 2.1 of the License,
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* the Free Software Foundation; either version 2.1 of the License,
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* capable of executing software compile for EDK 2.1 using GCC. It has the
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* capable of executing software compile for EDK 2.1 using GCC. It has the
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* capability of handling interrupts as well as exceptions.
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* capability of handling interrupts as well as exceptions.
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*
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*
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* HISTORY
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* HISTORY
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* $Log: not supported by cvs2svn $
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* $Log: not supported by cvs2svn $
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* Revision 1.1 2007/03/09 17:52:17 sybreon
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* initial import
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*
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*
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*/
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*/
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module aeMB_core (/*AUTOARG*/
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module aeMB_core (/*AUTOARG*/
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// Outputs
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// Outputs
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iwb_we_o, iwb_stb_o, iwb_sel_o, iwb_adr_o, dwb_we_o, dwb_stb_o,
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iwb_stb_o, iwb_adr_o, dwb_we_o, dwb_stb_o, dwb_dat_o, dwb_adr_o,
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dwb_dat_o, dwb_adr_o,
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// Inputs
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// Inputs
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sys_run_i, sys_rst_i, sys_int_i, sys_exc_i, sys_clk_i, iwb_dat_i,
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sys_run_i, sys_rst_i, sys_int_i, sys_exc_i, sys_clk_i, iwb_dat_i,
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iwb_ack_i, dwb_dat_i, dwb_ack_i
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iwb_ack_i, dwb_dat_i, dwb_ack_i
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);
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);
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// Instruction WB address space
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// Instruction WB address space
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output [DSIZ-1:0] dwb_adr_o; // From aslu of aeMB_aslu.v
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output [DSIZ-1:0] dwb_adr_o; // From aslu of aeMB_aslu.v
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output [31:0] dwb_dat_o; // From regfile of aeMB_regfile.v
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output [31:0] dwb_dat_o; // From regfile of aeMB_regfile.v
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output dwb_stb_o; // From decode of aeMB_decode.v
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output dwb_stb_o; // From decode of aeMB_decode.v
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output dwb_we_o; // From decode of aeMB_decode.v
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output dwb_we_o; // From decode of aeMB_decode.v
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output [ISIZ-1:0] iwb_adr_o; // From fetch of aeMB_fetch.v
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output [ISIZ-1:0] iwb_adr_o; // From fetch of aeMB_fetch.v
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output [3:0] iwb_sel_o; // From decode of aeMB_decode.v
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output iwb_stb_o; // From decode of aeMB_decode.v
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output iwb_stb_o; // From decode of aeMB_decode.v
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output iwb_we_o; // From decode of aeMB_decode.v
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// End of automatics
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// End of automatics
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/*AUTOINPUT*/
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/*AUTOINPUT*/
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// Beginning of automatic inputs (from unused autoinst inputs)
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// Beginning of automatic inputs (from unused autoinst inputs)
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input dwb_ack_i; // To control of aeMB_control.v
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input dwb_ack_i; // To control of aeMB_control.v
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input [31:0] dwb_dat_i; // To regfile of aeMB_regfile.v, ...
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input [31:0] dwb_dat_i; // To regfile of aeMB_regfile.v, ...
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wire [1:0] rFSM; // From control of aeMB_control.v
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wire [1:0] rFSM; // From control of aeMB_control.v
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wire [15:0] rIMM; // From decode of aeMB_decode.v
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wire [15:0] rIMM; // From decode of aeMB_decode.v
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wire rIWBSTB; // From decode of aeMB_decode.v
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wire rIWBSTB; // From decode of aeMB_decode.v
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wire rLNK; // From decode of aeMB_decode.v
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wire rLNK; // From decode of aeMB_decode.v
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wire [1:0] rMXALU; // From decode of aeMB_decode.v
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wire [1:0] rMXALU; // From decode of aeMB_decode.v
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wire [1:0] rMXLDST; // From decode of aeMB_decode.v
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wire [1:0] rMXSRC; // From decode of aeMB_decode.v
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wire [1:0] rMXSRC; // From decode of aeMB_decode.v
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wire [1:0] rMXTGT; // From decode of aeMB_decode.v
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wire [1:0] rMXTGT; // From decode of aeMB_decode.v
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wire [5:0] rOPC; // From decode of aeMB_decode.v
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wire [5:0] rOPC; // From decode of aeMB_decode.v
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wire [31:0] rPC; // From fetch of aeMB_fetch.v
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wire [31:0] rPC; // From fetch of aeMB_fetch.v
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wire [31:0] rPCNXT; // From fetch of aeMB_fetch.v
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wire [31:0] rPCNXT; // From fetch of aeMB_fetch.v
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.rOPC (rOPC[5:0]),
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.rOPC (rOPC[5:0]),
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.rPC (rPC[31:0]),
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.rPC (rPC[31:0]),
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.rIMM (rIMM[15:0]),
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.rIMM (rIMM[15:0]),
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.rRD (rRD[4:0]),
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.rRD (rRD[4:0]),
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.rRA (rRA[4:0]),
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.rRA (rRA[4:0]),
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.rMXLDST (rMXLDST[1:0]),
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.nclk (nclk),
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.nclk (nclk),
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.nrst (nrst),
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.nrst (nrst),
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.drun (drun),
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.drun (drun),
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.drst (drst));
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.drst (drst));
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.rIWBSTB (rIWBSTB),
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.rIWBSTB (rIWBSTB),
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.rDLY (rDLY),
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.rDLY (rDLY),
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.rLNK (rLNK),
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.rLNK (rLNK),
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.rBRA (rBRA),
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.rBRA (rBRA),
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.rRWE (rRWE),
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.rRWE (rRWE),
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.iwb_sel_o (iwb_sel_o[3:0]),
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.rMXLDST (rMXLDST[1:0]),
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.iwb_stb_o (iwb_stb_o),
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.iwb_stb_o (iwb_stb_o),
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.iwb_we_o (iwb_we_o),
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.dwb_stb_o (dwb_stb_o),
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.dwb_stb_o (dwb_stb_o),
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.dwb_we_o (dwb_we_o),
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.dwb_we_o (dwb_we_o),
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// Inputs
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// Inputs
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.rREGA (rREGA[31:0]),
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.rREGA (rREGA[31:0]),
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.rRESULT (rRESULT[31:0]),
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.rRESULT (rRESULT[31:0]),
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