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// $Id: aeMB_regf.v,v 1.1 2007-11-02 03:25:41 sybreon Exp $
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// $Id: aeMB_regf.v,v 1.2 2007-11-09 20:51:52 sybreon Exp $
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//
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//
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// AEMB REGISTER FILE
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// AEMB REGISTER FILE
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//
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//
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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//
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//
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// License along with this library; if not, write to the Free Software
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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// USA
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// USA
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2007/11/02 03:25:41 sybreon
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// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
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// Fixed various minor data hazard bugs.
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// Code compatible with -O0/1/2/3/s generated code.
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//
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module aeMB_regf (/*AUTOARG*/
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module aeMB_regf (/*AUTOARG*/
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// Outputs
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// Outputs
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rREGA, rREGB, rDWBDI, dwb_dat_o,
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rREGA, rREGB, rDWBDI, dwb_dat_o, fsl_dat_o,
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// Inputs
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// Inputs
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rOPC, rRA, rRB, rRW, rRD, rMXDST, rPCLNK, rRESULT, rDWBSEL, rBRA,
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rOPC, rRA, rRB, rRW, rRD, rMXDST, rPCLNK, rRESULT, rDWBSEL, rBRA,
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rDLY, dwb_dat_i, gclk, grst, gena
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rDLY, dwb_dat_i, fsl_dat_i, gclk, grst, gena
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);
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);
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// INTERNAL
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// INTERNAL
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output [31:0] rREGA, rREGB;
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output [31:0] rREGA, rREGB;
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output [31:0] rDWBDI;
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output [31:0] rDWBDI;
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input [5:0] rOPC;
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input [5:0] rOPC;
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// DATA WISHBONE
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// DATA WISHBONE
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output [31:0] dwb_dat_o;
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output [31:0] dwb_dat_o;
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input [31:0] dwb_dat_i;
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input [31:0] dwb_dat_i;
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// FSL WISHBONE
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output [31:0] fsl_dat_o;
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input [31:0] fsl_dat_i;
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// SYSTEM
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// SYSTEM
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input gclk, grst, gena;
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input gclk, grst, gena;
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// --- LOAD SIZER ----------------------------------------------
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// --- LOAD SIZER ----------------------------------------------
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// Moves the data bytes around depending on the size of the
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// Moves the data bytes around depending on the size of the
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// operation.
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// operation.
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wire [31:0] wDWBDI = dwb_dat_i; // FIXME: Endian
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wire [31:0] wDWBDI = dwb_dat_i; // FIXME: Endian
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wire [31:0] wFSLDI = fsl_dat_i; // FIXME: Endian
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reg [31:0] rDWBDI;
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reg [31:0] rDWBDI;
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always @(/*AUTOSENSE*/rDWBSEL or wDWBDI)
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always @(/*AUTOSENSE*/rDWBSEL or wDWBDI or wFSLDI)
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case (rDWBSEL)
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case (rDWBSEL)
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// 8'bit
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// 8'bit
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4'h8: rDWBDI <= {24'd0, wDWBDI[31:24]};
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4'h8: rDWBDI <= {24'd0, wDWBDI[31:24]};
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4'h4: rDWBDI <= {24'd0, wDWBDI[23:16]};
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4'h4: rDWBDI <= {24'd0, wDWBDI[23:16]};
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4'h2: rDWBDI <= {24'd0, wDWBDI[15:8]};
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4'h2: rDWBDI <= {24'd0, wDWBDI[15:8]};
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// 16'bit
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// 16'bit
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4'hC: rDWBDI <= {16'd0, wDWBDI[31:16]};
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4'hC: rDWBDI <= {16'd0, wDWBDI[31:16]};
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4'h3: rDWBDI <= {16'd0, wDWBDI[15:0]};
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4'h3: rDWBDI <= {16'd0, wDWBDI[15:0]};
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// 32'bit
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// 32'bit
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4'hF: rDWBDI <= wDWBDI;
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4'hF: rDWBDI <= wDWBDI;
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// FSL
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4'h0: rDWBDI <= wFSLDI;
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// Undefined
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// Undefined
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default: rDWBDI <= 32'hX;
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default: rDWBDI <= 32'hX;
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endcase
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endcase
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// --- GENERAL PURPOSE REGISTERS (R0-R31) -----------------------
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// --- GENERAL PURPOSE REGISTERS (R0-R31) -----------------------
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// --- STORE SIZER ---------------------------------------------
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// --- STORE SIZER ---------------------------------------------
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// Replicates the data bytes across depending on the size of the
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// Replicates the data bytes across depending on the size of the
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// operation.
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// operation.
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wire [31:0] xFSL;
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wire fFFWD_M = (rRA == rRW) & (rMXDST == 2'o2) & fRDWE;
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wire fFFWD_R = (rRA == rRW) & (rMXDST == 2'o0) & fRDWE;
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assign fsl_dat_o = rDWBDO;
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assign xFSL = (fFFWD_M) ? rDWBDI :
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(fFFWD_R) ? rRESULT :
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rREGA;
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wire [31:0] xDST;
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wire [31:0] xDST;
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wire fDFWD_M = (rRW == rRD) & (rMXDST == 2'o2) & fRDWE;
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wire fDFWD_M = (rRW == rRD) & (rMXDST == 2'o2) & fRDWE;
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wire fDFWD_R = (rRW == rRD) & (rMXDST == 2'o0) & fRDWE;
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wire fDFWD_R = (rRW == rRD) & (rMXDST == 2'o0) & fRDWE;
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reg [31:0] rDWBDO, xDWBDO;
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reg [31:0] rDWBDO, xDWBDO;
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assign dwb_dat_o = rDWBDO;
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assign dwb_dat_o = rDWBDO;
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assign xDST = (fDFWD_M) ? rDWBDI :
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assign xDST = (fDFWD_M) ? rDWBDI :
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(fDFWD_R) ? rRESULT :
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(fDFWD_R) ? rRESULT :
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rREGD;
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rREGD;
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always @(/*AUTOSENSE*/rOPC or xDST)
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always @(/*AUTOSENSE*/rOPC or xDST or xFSL)
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case (rOPC[1:0])
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case (rOPC[1:0])
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// 8'bit
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// 8'bit
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2'h0: xDWBDO <= {(4){xDST[7:0]}};
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2'h0: xDWBDO <= {(4){xDST[7:0]}};
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// 16'bit
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// 16'bit
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2'h1: xDWBDO <= {(2){xDST[15:0]}};
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2'h1: xDWBDO <= {(2){xDST[15:0]}};
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// 32'bit
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// 32'bit
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2'h2: xDWBDO <= xDST;
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2'h2: xDWBDO <= xDST;
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default: xDWBDO <= 32'hX;
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// FSL
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2'h3: xDWBDO <= xFSL;
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//default: xDWBDO <= 32'hX;
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endcase // case (rOPC[1:0])
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endcase // case (rOPC[1:0])
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always @(posedge gclk)
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always @(posedge gclk)
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if (grst) begin
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if (grst) begin
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/*AUTORESET*/
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/*AUTORESET*/
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