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// $Id: edk32.v,v 1.8 2007-11-18 19:41:45 sybreon Exp $
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// $Id: edk32.v,v 1.9 2007-11-20 18:36:00 sybreon Exp $
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//
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//
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// AEMB EDK 3.2 Compatible Core TEST
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// AEMB EDK 3.2 Compatible Core TEST
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//
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//
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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//
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//
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//
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//
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// You should have received a copy of the GNU Lesser General Public
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// You should have received a copy of the GNU Lesser General Public
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// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
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// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.8 2007/11/18 19:41:45 sybreon
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// Minor simulation fixes.
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//
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// Revision 1.7 2007/11/14 22:11:41 sybreon
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// Revision 1.7 2007/11/14 22:11:41 sybreon
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// Added posedge/negedge bus interface.
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// Added posedge/negedge bus interface.
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// Modified interrupt test system.
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// Modified interrupt test system.
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//
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//
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// Revision 1.6 2007/11/13 23:37:28 sybreon
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// Revision 1.6 2007/11/13 23:37:28 sybreon
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integer theend;
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integer theend;
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always #5 sys_clk_i = ~sys_clk_i;
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always #5 sys_clk_i = ~sys_clk_i;
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initial begin
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initial begin
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$dumpfile("dump.vcd");
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//$dumpfile("dump.vcd");
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$dumpvars(1,dut);
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//$dumpvars(1,dut);
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//$dumpvars(1,dut.scon);
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end
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end
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initial begin
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initial begin
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seed = randseed;
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seed = randseed;
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theend = 0;
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theend = 0;
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dwb_ack_i = 0;
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dwb_ack_i = 0;
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iwb_ack_i = 0;
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iwb_ack_i = 0;
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fsl_ack_i = 0;
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fsl_ack_i = 0;
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end
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end
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assign {dwb_dat_i[7:0],dwb_dat_i[15:8],dwb_dat_i[23:16],dwb_dat_i[31:24]} = ram[dadr];
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assign dwb_dat_t = ram[dwb_adr_o];
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assign {iwb_dat_i[7:0],iwb_dat_i[15:8],iwb_dat_i[23:16],iwb_dat_i[31:24]} = ram[iadr];
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assign iwb_dat_i = ram[iadr];
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assign {dwb_dat_t} = ram[dwb_adr_o];
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assign dwb_dat_i = ram[dadr];
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assign fsl_dat_i = fsl_adr_o;
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assign fsl_dat_i = fsl_adr_o;
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//`define POSEDGE
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//`define POSEDGE
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`ifdef POSEDGE
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`ifdef POSEDGE
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iadr <= #1 iwb_adr_o;
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iadr <= #1 iwb_adr_o;
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dadr <= #1 dwb_adr_o;
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dadr <= #1 dwb_adr_o;
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if (dwb_we_o & dwb_stb_o) begin
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if (dwb_we_o & dwb_stb_o) begin
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case (dwb_sel_o)
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case (dwb_sel_o)
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4'h1: ram[dwb_adr_o] <= {dwb_dat_o[7:0],dwb_dat_t[23:0]};
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4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]};
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4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:24],dwb_dat_o[15:8],dwb_dat_t[15:0]};
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4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]};
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4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:16],dwb_dat_o[23:16],dwb_dat_t[7:0]};
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4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]};
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4'h8: ram[dwb_adr_o] <= {dwb_dat_t[31:8],dwb_dat_o[31:24]};
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4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]};
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4'h3: ram[dwb_adr_o] <= {dwb_dat_o[7:0],dwb_dat_o[15:8],dwb_dat_t[15:0]};
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4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]};
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4'hC: ram[dwb_adr_o] <= {dwb_dat_t[31:16],dwb_dat_o[23:16],dwb_dat_o[31:24]};
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4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]};
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4'hF: ram[dwb_adr_o] <= {dwb_dat_o[7:0],dwb_dat_o[15:8],dwb_dat_o[23:16],dwb_dat_o[31:24]};
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4'hF: ram[dwb_adr_o] <= {dwb_dat_o};
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endcase // case (dwb_sel_o)
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endcase // case (dwb_sel_o)
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end // if (dwb_we_o & dwb_stb_o)
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end // if (dwb_we_o & dwb_stb_o)
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end // always @ (negedge sys_clk_i)
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end // always @ (negedge sys_clk_i)
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`else // !`ifdef POSEDGE
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`else // !`ifdef POSEDGE
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iadr <= #1 iwb_adr_o;
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iadr <= #1 iwb_adr_o;
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dadr <= #1 dwb_adr_o;
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dadr <= #1 dwb_adr_o;
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if (dwb_we_o & dwb_stb_o) begin
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if (dwb_we_o & dwb_stb_o) begin
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case (dwb_sel_o)
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case (dwb_sel_o)
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4'h1: ram[dwb_adr_o] <= {dwb_dat_o[7:0],dwb_dat_t[23:0]};
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4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]};
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4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:24],dwb_dat_o[15:8],dwb_dat_t[15:0]};
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4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]};
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4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:16],dwb_dat_o[23:16],dwb_dat_t[7:0]};
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4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]};
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4'h8: ram[dwb_adr_o] <= {dwb_dat_t[31:8],dwb_dat_o[31:24]};
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4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]};
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4'h3: ram[dwb_adr_o] <= {dwb_dat_o[7:0],dwb_dat_o[15:8],dwb_dat_t[15:0]};
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4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]};
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4'hC: ram[dwb_adr_o] <= {dwb_dat_t[31:16],dwb_dat_o[23:16],dwb_dat_o[31:24]};
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4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]};
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4'hF: ram[dwb_adr_o] <= {dwb_dat_o[7:0],dwb_dat_o[15:8],dwb_dat_o[23:16],dwb_dat_o[31:24]};
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4'hF: ram[dwb_adr_o] <= {dwb_dat_o};
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endcase // case (dwb_sel_o)
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endcase // case (dwb_sel_o)
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end // if (dwb_we_o & dwb_stb_o)
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end // if (dwb_we_o & dwb_stb_o)
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end // always @ (negedge sys_clk_i)
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end // always @ (negedge sys_clk_i)
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`endif // !`ifdef POSEDGE
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`endif // !`ifdef POSEDGE
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integer i;
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integer i;
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initial begin
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initial begin
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for (i=0;i<65535;i=i+1) begin
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for (i=0;i<65535;i=i+1) begin
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ram[i] <= $random;
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ram[i] <= $random;
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end
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end
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#1 $readmemh("aeMB.rom",ram);
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#1 $readmemh("dump.rom",ram);
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end
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end
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// DISPLAY OUTPUTS ///////////////////////////////////////////////////
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// DISPLAY OUTPUTS ///////////////////////////////////////////////////
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//assign dut.rRESULT = dut.rSIMM;
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//assign dut.rRESULT = dut.rSIMM;
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$write ("\n", ($stime/10));
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$write ("\n", ($stime/10));
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$writeh ("\tPC=", {iwb_adr_o,2'd0});
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$writeh ("\tPC=", {iwb_adr_o,2'd0});
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// DECODE
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// DECODE
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$writeh ("\t");
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$writeh ("\t");
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/*
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case (dut.bpcu.rATOM)
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2'o2, 2'o1: $write("/");
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2'o0, 2'o3: $write("\\");
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endcase // case (dut.bpcu.rATOM)
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*/
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case ({dut.rBRA, dut.rDLY})
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case ({dut.rBRA, dut.rDLY})
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2'b00: $write(" ");
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2'b00: $write(" ");
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2'b01: $write(".");
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2'b01: $write(".");
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2'b10: $write("-");
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2'b10: $write("-");
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