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/*
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/*
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* $Id: aeMB_aslu.v,v 1.8 2007-04-30 15:56:50 sybreon Exp $
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* $Id: aeMB_aslu.v,v 1.9 2007-05-17 09:08:21 sybreon Exp $
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*
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*
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* AEMB Arithmetic Shift Logic Unit
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* AEMB Arithmetic Shift Logic Unit
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* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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*
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*
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* This library is free software; you can redistribute it and/or
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* This library is free software; you can redistribute it and/or
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* Arithmetic, shift and logic execution unit. It also performs the
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* Arithmetic, shift and logic execution unit. It also performs the
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* necessary calculations for branch and load/store targets.
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* necessary calculations for branch and load/store targets.
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*
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*
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* HISTORY
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* HISTORY
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* $Log: not supported by cvs2svn $
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* $Log: not supported by cvs2svn $
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* Revision 1.8 2007/04/30 15:56:50 sybreon
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* Removed byte acrobatics.
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*
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* Revision 1.7 2007/04/27 00:23:55 sybreon
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* Revision 1.7 2007/04/27 00:23:55 sybreon
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* Added code documentation.
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* Added code documentation.
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* Improved size & speed of rtl/verilog/aeMB_aslu.v
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* Improved size & speed of rtl/verilog/aeMB_aslu.v
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*
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*
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* Revision 1.6 2007/04/26 14:29:53 sybreon
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* Revision 1.6 2007/04/26 14:29:53 sybreon
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module aeMB_aslu (/*AUTOARG*/
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module aeMB_aslu (/*AUTOARG*/
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// Outputs
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// Outputs
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dwb_adr_o, dwb_sel_o, rRESULT, rDWBSEL,
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dwb_adr_o, dwb_sel_o, rRESULT, rDWBSEL,
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// Inputs
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// Inputs
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sDWBDAT, rBRA, rDLY, rREGA, rREGB, rSIMM, rMXSRC, rMXTGT, rMXALU,
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sDWBDAT, rBRA, rDLY, rREGA, rREGB, rSIMM, rMXSRC, rMXTGT, rMXALU,
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rOPC, rPC, rIMM, rRD, rRA, rMXLDST, nclk, nrst, drun, nrun
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rOPC, rPC, rIMM, rRD, rRA, rMXLDST, nclk, prst, drun, prun
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);
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);
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parameter DSIZ = 32;
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parameter DSIZ = 32;
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output [DSIZ-1:0] dwb_adr_o;
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output [DSIZ-1:0] dwb_adr_o;
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output [3:0] dwb_sel_o;
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output [3:0] dwb_sel_o;
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input [31:0] rPC;
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input [31:0] rPC;
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input [15:0] rIMM;
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input [15:0] rIMM;
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input [4:0] rRD, rRA;
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input [4:0] rRD, rRA;
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input [1:0] rMXLDST;
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input [1:0] rMXLDST;
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input nclk, nrst, drun, nrun;
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input nclk, prst, drun, prun;
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reg [31:0] rRESULT, xRESULT;
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reg [31:0] rRESULT, xRESULT;
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reg rMSR_C, xMSR_C;
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reg rMSR_C, xMSR_C;
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/**
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/**
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endcase // case (rMXALU)
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endcase // case (rMXALU)
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end
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end
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// PIPELINE REGISTER //////////////////////////////////////////////////
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// PIPELINE REGISTER //////////////////////////////////////////////////
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always @(negedge nclk or negedge nrst)
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always @(negedge nclk)
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if (!nrst) begin
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if (prst) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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rDWBSEL <= 4'h0;
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rDWBSEL <= 4'h0;
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rMSR_C <= 1'h0;
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rMSR_C <= 1'h0;
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rRESULT <= 32'h0;
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rRESULT <= 32'h0;
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// End of automatics
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// End of automatics
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end else if (nrun) begin
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end else if (prun) begin
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rRESULT <= #1 xRESULT;
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rRESULT <= #1 xRESULT;
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rMSR_C <= #1 xMSR_C;
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rMSR_C <= #1 xMSR_C;
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rDWBSEL <= #1 xDWBSEL;
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rDWBSEL <= #1 xDWBSEL;
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end
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end
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