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// -*- Mode: Verilog -*-
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// -*- Mode: Verilog -*-
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// Filename : aeMB_aslu.v
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// Filename : aeMB_aslu.v
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// Description : AEMB Arithmetic Shift Logic Unit
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// Description : AEMB Arithmetic Shift Logic Unit
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// Author : Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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// Author : Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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// Created On : Sat Dec 30 06:03:24 2006
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// Created On : Sat Dec 30 06:03:24 2006
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// Last Modified By: Shawn Tan
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// Last Modified By: $Author: sybreon $
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// Last Modified On: 2006-12-30
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// Last Modified On: $Date: 2007-04-04 06:11:05 $
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// Update Count : 0
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// Update Count : $Revision
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// Status : Unknown, Use with caution!
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// Status : $State: Exp $
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/*
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/*
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* $Id: aeMB_aslu.v,v 1.2 2007-04-03 14:46:26 sybreon Exp $
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* $Id: aeMB_aslu.v,v 1.3 2007-04-04 06:11:05 sybreon Exp $
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*
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*
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* AEMB Arithmetic Shift Logic Unit
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* Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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* Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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*
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*
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* This library is free software; you can redistribute it and/or modify it
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* This library is free software; you can redistribute it and/or modify it
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* under the terms of the GNU Lesser General Public License as published by
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* under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation; either version 2.1 of the License,
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* the Free Software Foundation; either version 2.1 of the License,
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* DESCRIPTION
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* DESCRIPTION
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* Arithmetic, shift and logic execution unit
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* Arithmetic, shift and logic execution unit
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*
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*
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* HISTORY
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* HISTORY
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* $Log: not supported by cvs2svn $
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* $Log: not supported by cvs2svn $
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* Revision 1.2 2007/04/03 14:46:26 sybreon
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* Fixed endian correction issues on data bus.
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*
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* Revision 1.1 2007/03/09 17:52:17 sybreon
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* Revision 1.1 2007/03/09 17:52:17 sybreon
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* initial import
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* initial import
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*
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*
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*
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*/
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*/
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module aeMB_aslu (/*AUTOARG*/
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module aeMB_aslu (/*AUTOARG*/
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// Outputs
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// Outputs
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dwb_adr_o, rRESULT,
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dwb_adr_o, rRESULT,
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// Inputs
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// Inputs
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dwb_dat_i, rBRA, rDLY, rREGA, rREGB, rSIMM, rMXSRC, rMXTGT, rMXALU,
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dwb_dat_i, rBRA, rDLY, rREGA, rREGB, rSIMM, rMXSRC, rMXTGT, rMXALU,
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rOPC, rPC, rIMM, rRD, rRA, nclk, nrst, drun, drst
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rOPC, rPC, rIMM, rRD, rRA, rMXLDST, nclk, nrst, drun, drst
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);
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);
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parameter DSIZ = 32;
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parameter DSIZ = 32;
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output [DSIZ-1:0] dwb_adr_o;
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output [DSIZ-1:0] dwb_adr_o;
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input [31:0] dwb_dat_i;
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input [31:0] dwb_dat_i;
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input [1:0] rMXALU;
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input [1:0] rMXALU;
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input [5:0] rOPC;
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input [5:0] rOPC;
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input [31:0] rPC;
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input [31:0] rPC;
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input [15:0] rIMM;
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input [15:0] rIMM;
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input [4:0] rRD, rRA;
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input [4:0] rRD, rRA;
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input [1:0] rMXLDST;
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input nclk, nrst, drun, drst;
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input nclk, nrst, drun, drst;
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reg [31:0] rRESULT;
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reg [31:0] rRESULT;
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reg rMSR_C;
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reg rMSR_C;
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(rMXTGT == 2'b10) ? rRESULT :
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(rMXTGT == 2'b10) ? rRESULT :
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(rMXTGT == 2'b01) ? rSIMM :
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(rMXTGT == 2'b01) ? rSIMM :
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rREGB;
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rREGB;
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// ARITHMETIC
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// ARITHMETIC
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//wire wADDC_ = (rOPC[1] & (rMXLDST == 2'o0)) ? rMSR_C : 1'b0;
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wire wADDC_ = (rOPC[1]) ? rMSR_C : 1'b0;
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wire wADDC_ = (rOPC[1]) ? rMSR_C : 1'b0;
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wire wSUBC_ = (rOPC[1]) ? rMSR_C : 1'b1;
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wire wSUBC_ = (rOPC[1]) ? rMSR_C : 1'b1;
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wire wADDC, wSUBC, wRES_AC;
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wire wADDC, wSUBC, wRES_AC,wCMPC;
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wire [31:0] wADD,wSUB,wRES_A;
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wire wCMPU;
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wire [31:0] wADD,wSUB,wRES_A,wCMP;
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// TODO: verify signed compare
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assign wCMPU = (rIMM[1]) ? ~(wOPB >= wOPA) :
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~(((wOPB >= wOPA) & (wOPB[31]==wOPA[31])) | (~wOPB[31] & wOPA[31]));
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assign {wCMPC,wCMP} = {wSUBC,wCMPU,wSUB[30:0]};
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assign {wADDC,wADD} = (wOPB + wOPA) + wADDC_;
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assign {wADDC,wADD} = (wOPB + wOPA) + wADDC_;
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assign {wSUBC,wSUB} = (wOPB + ~wOPA) + wSUBC_;
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assign {wSUBC,wSUB} = (wOPB + ~wOPA) + wSUBC_;
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reg rRES_AC;
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reg rRES_AC;
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reg [31:0] rRES_A;
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reg [31:0] rRES_A;
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always @(/*AUTOSENSE*/rOPC or wADD or wADDC or wSUB or wSUBC)
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always @(/*AUTOSENSE*/rIMM or rOPC or wADD or wADDC or wCMP
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{rRES_AC,rRES_A} <= #1 (rOPC[0] & ~rOPC[5]) ? {~wSUBC,wSUB} : {wADDC,wADD};
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or wCMPC or wSUB or wSUBC)
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//{rRES_AC,rRES_A} <= #1 (rOPC[0] & ~rOPC[5]) ? {~wSUBC,wSUB} : {wADDC,wADD};
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case ({rOPC[5],rOPC[3],rOPC[0],rIMM[0]})
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4'h2, 4'h6, 4'h7: {rRES_AC,rRES_A} <= #1 {~wSUBC,wSUB}; // SUB
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4'h3: {rRES_AC,rRES_A} <= #1 {~wCMPC,wCMP}; // CMP
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default: {rRES_AC,rRES_A} <= #1 {wADDC,wADD};
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endcase // case ({rOPC[5],rOPC[0]})
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// LOGIC
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// LOGIC
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wire [31:0] wOR = wOPA | wOPB;
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wire [31:0] wOR = wOPA | wOPB;
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wire [31:0] wAND = wOPA & wOPB;
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wire [31:0] wAND = wOPA & wOPB;
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wire [31:0] wXOR = wOPA ^ wOPB;
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wire [31:0] wXOR = wOPA ^ wOPB;
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//rMSR_C;
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//rMSR_C;
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endcase // case(rMXALU)
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endcase // case(rMXALU)
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end
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end
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// DWB I/F
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// DWB I/F
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assign dwb_adr_o = rRESULT;
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//assign dwb_adr_o = rRESULT;
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//{rRESULT[DSIZ-1:2],2'b00};
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assign dwb_adr_o = {rRESULT[DSIZ-1:2],2'b00};
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endmodule // aeMB_aslu
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endmodule // aeMB_aslu
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