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/*
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/*
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* $Id: aeMB_control.v,v 1.4 2007-04-27 00:23:55 sybreon Exp $
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* $Id: aeMB_control.v,v 1.5 2007-05-16 12:32:21 sybreon Exp $
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*
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*
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* AE68 System Control Unit
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* AE68 System Control Unit
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* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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*
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*
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* This library is free software; you can redistribute it and/or
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* This library is free software; you can redistribute it and/or
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* DESCRIPTION
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* DESCRIPTION
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* Controls the state of the processor.
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* Controls the state of the processor.
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*
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*
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* HISTORY
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* HISTORY
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* $Log: not supported by cvs2svn $
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* $Log: not supported by cvs2svn $
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* Revision 1.4 2007/04/27 00:23:55 sybreon
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* Added code documentation.
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* Improved size & speed of rtl/verilog/aeMB_aslu.v
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*
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* Revision 1.3 2007/04/11 04:30:43 sybreon
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* Revision 1.3 2007/04/11 04:30:43 sybreon
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* Added pipeline stalling from incomplete bus cycles.
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* Added pipeline stalling from incomplete bus cycles.
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* Separated sync and async portions of code.
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* Separated sync and async portions of code.
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*
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*
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* Revision 1.2 2007/04/04 14:08:34 sybreon
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* Revision 1.2 2007/04/04 14:08:34 sybreon
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Pipeline bubbles are introduced during a branch or interrupt.
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Pipeline bubbles are introduced during a branch or interrupt.
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TODO: Implement interrupt bubble.
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TODO: Implement interrupt bubble.
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*/
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*/
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reg [1:0] rRUN;
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reg [1:0] rRUN, xRUN;
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assign {drun,frun} = rRUN;
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assign {drun,frun} = rRUN;
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always @(/*AUTOSENSE*/rBRA or rDLY) begin
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xRUN <= {~(rBRA ^ rDLY), ~rBRA};
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end
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always @(posedge nclk or negedge nrst)
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always @(posedge nclk or negedge nrst)
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if (!nrst) begin
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if (!nrst) begin
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rRUN <= 2'h3;
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rRUN <= 2'h3;
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/*AUTORESET*/
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/*AUTORESET*/
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end else begin
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end else begin
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rRUN <= #1 {~(rBRA ^ rDLY), ~rBRA};
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rRUN <= #1 xRUN;
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end
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end
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/**
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/**
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Clock/Reset
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Clock/Reset
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-----------
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-----------
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