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https://opencores.org/ocsvn/aemb/aemb/trunk
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/*
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/*
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* $Id: aeMB_regfile.v,v 1.7 2007-04-11 16:30:06 sybreon Exp $
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* $Id: aeMB_regfile.v,v 1.8 2007-04-12 20:21:33 sybreon Exp $
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*
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*
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* AEMB Register File
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* AEMB Register File
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* Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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* Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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*
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*
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* This library is free software; you can redistribute it and/or modify it
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* This library is free software; you can redistribute it and/or modify it
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* special actions during hardware exception/interrupts. Data forwarding
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* special actions during hardware exception/interrupts. Data forwarding
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* is also taken care of inside here to simplify decode logic.
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* is also taken care of inside here to simplify decode logic.
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*
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*
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* HISTORY
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* HISTORY
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* $Log: not supported by cvs2svn $
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* $Log: not supported by cvs2svn $
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* Revision 1.7 2007/04/11 16:30:06 sybreon
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* Cosmetic changes
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*
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* Revision 1.6 2007/04/11 04:30:43 sybreon
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* Revision 1.6 2007/04/11 04:30:43 sybreon
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* Added pipeline stalling from incomplete bus cycles.
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* Added pipeline stalling from incomplete bus cycles.
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* Separated sync and async portions of code.
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* Separated sync and async portions of code.
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*
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*
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* Revision 1.5 2007/04/04 14:08:34 sybreon
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* Revision 1.5 2007/04/04 14:08:34 sybreon
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rMEMB[i] <= 0;
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rMEMB[i] <= 0;
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rMEMD[i] <= 0;
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rMEMD[i] <= 0;
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end
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end
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end
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end
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always @(negedge nclk) begin
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if ((fWE & (rRD_== 5'd0)) || (fLNK & (rRD_== 5'd0)) || (fLD & (rRD_== 5'd0))) $displayh("!!! Warning: Write to R0 !!!");
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end
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endmodule // aeMB_regfile
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endmodule // aeMB_regfile
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// Local Variables:
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// Local Variables:
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// verilog-library-directories:(".")
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// verilog-library-directories:(".")
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