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/*
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/*
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* $Id: aeMB_regfile.v,v 1.10 2007-04-25 22:52:53 sybreon Exp $
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* $Id: aeMB_regfile.v,v 1.11 2007-04-26 14:29:53 sybreon Exp $
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*
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*
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* AEMB Register File
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* AEMB Register File
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* Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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* Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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*
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*
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* This library is free software; you can redistribute it and/or modify it
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* This library is free software; you can redistribute it and/or modify it
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* special actions during hardware exception/interrupts. Data forwarding
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* special actions during hardware exception/interrupts. Data forwarding
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* is also taken care of inside here to simplify decode logic.
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* is also taken care of inside here to simplify decode logic.
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*
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*
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* HISTORY
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* HISTORY
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* $Log: not supported by cvs2svn $
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* $Log: not supported by cvs2svn $
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* Revision 1.10 2007/04/25 22:52:53 sybreon
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* Fixed minor simulation bug.
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*
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* Revision 1.9 2007/04/25 22:15:04 sybreon
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* Revision 1.9 2007/04/25 22:15:04 sybreon
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* Added support for 8-bit and 16-bit data types.
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* Added support for 8-bit and 16-bit data types.
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*
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*
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* Revision 1.8 2007/04/12 20:21:33 sybreon
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* Revision 1.8 2007/04/12 20:21:33 sybreon
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* Moved testbench into /sim/verilog.
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* Moved testbench into /sim/verilog.
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assign dwb_dat_o = {rDWBDAT[7:0],rDWBDAT[15:8],rDWBDAT[23:16],rDWBDAT[31:24]};
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assign dwb_dat_o = {rDWBDAT[7:0],rDWBDAT[15:8],rDWBDAT[23:16],rDWBDAT[31:24]};
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assign wDWBDAT = {dwb_dat_i[7:0],dwb_dat_i[15:8],dwb_dat_i[23:16],dwb_dat_i[31:24]};
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assign wDWBDAT = {dwb_dat_i[7:0],dwb_dat_i[15:8],dwb_dat_i[23:16],dwb_dat_i[31:24]};
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always @(/*AUTOSENSE*/rDWBSEL or wDWBDAT)
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always @(/*AUTOSENSE*/rDWBSEL or wDWBDAT)
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case (rDWBSEL)
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case (rDWBSEL)
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4'hF: sDWBDAT <= wDWBDAT;
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default: sDWBDAT <= wDWBDAT;
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4'hC: sDWBDAT <= {16'd0,wDWBDAT[31:16]};
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4'hC: sDWBDAT <= {16'd0,wDWBDAT[31:16]};
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4'h3: sDWBDAT <= {16'd0,wDWBDAT[15:0]};
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4'h3: sDWBDAT <= {16'd0,wDWBDAT[15:0]};
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4'h8: sDWBDAT <= {24'd0,wDWBDAT[31:24]};
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4'h8: sDWBDAT <= {24'd0,wDWBDAT[31:24]};
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4'h4: sDWBDAT <= {24'd0,wDWBDAT[23:16]};
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4'h4: sDWBDAT <= {24'd0,wDWBDAT[23:16]};
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4'h2: sDWBDAT <= {24'd0,wDWBDAT[15:8]};
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4'h2: sDWBDAT <= {24'd0,wDWBDAT[15:8]};
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4'h1: sDWBDAT <= {24'd0,wDWBDAT[7:0]};
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4'h1: sDWBDAT <= {24'd0,wDWBDAT[7:0]};
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default: sDWBDAT <= 32'h0;
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//default: sDWBDAT <= 32'h0;
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endcase // case (rDWBSEL)
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endcase // case (rDWBSEL)
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// Forwarding Control
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// Forwarding Control
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wire fDFWD = (rRD == rRD_) & fWE;
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wire fDFWD = (rRD == rRD_) & fWE;
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wire fMFWD = rDWBSTB & ~rDWBWE;
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wire fMFWD = rDWBSTB & ~rDWBWE;
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