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/*
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/*
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* $Id: aeMB_regfile.v,v 1.16 2007-05-15 22:44:57 sybreon Exp $
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* $Id: aeMB_regfile.v,v 1.17 2007-05-17 09:08:21 sybreon Exp $
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*
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*
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* AEMB Register File
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* AEMB Register File
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* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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*
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*
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* This library is free software; you can redistribute it and/or
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* This library is free software; you can redistribute it and/or
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* forwarding is also taken care of inside here to simplify decode
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* forwarding is also taken care of inside here to simplify decode
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* logic.
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* logic.
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*
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*
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* HISTORY
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* HISTORY
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* $Log: not supported by cvs2svn $
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* $Log: not supported by cvs2svn $
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* Revision 1.16 2007/05/15 22:44:57 sybreon
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* Corrected speed issues after rev 1.9 update.
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*
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* Revision 1.15 2007/04/30 15:56:50 sybreon
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* Revision 1.15 2007/04/30 15:56:50 sybreon
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* Removed byte acrobatics.
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* Removed byte acrobatics.
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*
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*
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* Revision 1.14 2007/04/27 15:15:49 sybreon
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* Revision 1.14 2007/04/27 15:15:49 sybreon
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* Fixed simulation bug.
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* Fixed simulation bug.
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module aeMB_regfile(/*AUTOARG*/
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module aeMB_regfile(/*AUTOARG*/
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// Outputs
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// Outputs
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dwb_dat_o, rREGA, rREGB, sDWBDAT,
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dwb_dat_o, rREGA, rREGB, sDWBDAT,
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// Inputs
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// Inputs
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dwb_dat_i, rDWBSTB, rDWBWE, rRA, rRB, rRD, rRESULT, rFSM, rPC,
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dwb_dat_i, rDWBSTB, rDWBWE, rRA, rRB, rRD, rRESULT, rFSM, rPC,
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rOPC, rDWBSEL, rLNK, rRWE, nclk, nrst, drun, nrun
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rOPC, rDWBSEL, rLNK, rRWE, nclk, prst, drun, prun
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);
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);
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// FIXME: This parameter is not used here.
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// FIXME: This parameter is not used here.
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parameter DSIZ = 32;
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parameter DSIZ = 32;
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// Data WB Signals
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// Data WB Signals
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input [1:0] rFSM;
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input [1:0] rFSM;
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input [31:0] rPC;
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input [31:0] rPC;
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input [5:0] rOPC;
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input [5:0] rOPC;
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input [3:0] rDWBSEL;
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input [3:0] rDWBSEL;
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input rLNK, rRWE;
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input rLNK, rRWE;
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input nclk, nrst, drun, nrun;
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input nclk, prst, drun, prun;
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/**
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/**
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Delay Latches
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Delay Latches
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----------
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----------
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The PC and RD are latched internally as it will be needed for
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The PC and RD are latched internally as it will be needed for
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RAM : 227 slices @ 141 MHz
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RAM : 227 slices @ 141 MHz
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*/
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*/
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reg [31:0] rMEMA[0:31], rMEMB[0:31], rMEMD[0:31];
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reg [31:0] rMEMA[0:31], rMEMB[0:31], rMEMD[0:31];
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wire [31:0] wDDAT, wREGA, wREGB, wREGD, wWBDAT;
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wire [31:0] wDDAT, wREGA, wREGB, wREGD, wWBDAT;
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wire wDWE = (fLD | fLNK | fWE) & |rRD_ & nrun;
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wire wDWE = (fLD | fLNK | fWE) & |rRD_ & prun;
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assign wDDAT = (fLD) ? sDWBDAT :
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assign wDDAT = (fLD) ? sDWBDAT :
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(fLNK) ? {rPC_,2'd0} :
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(fLNK) ? {rPC_,2'd0} :
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rRESULT;
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rRESULT;
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//assign wWBDAT = (fDFWD) ? wRESULT : wREGD;
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//assign wRESULT = (fMFWD) ? sDWBDAT : rRESULT;
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assign rREGA = rMEMA[rRA];
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assign rREGA = rMEMA[rRA];
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assign rREGB = rMEMB[rRB];
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assign rREGB = rMEMB[rRB];
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assign wREGD = rMEMD[rRD];
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assign wREGD = rMEMD[rRD];
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always @(negedge nclk)
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always @(negedge nclk)
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if (wDWE | !nrst) begin
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if (wDWE | prst) begin
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rMEMA[rRD_] <= wDDAT;
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rMEMA[rRD_] <= wDDAT;
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rMEMB[rRD_] <= wDDAT;
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rMEMB[rRD_] <= wDDAT;
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rMEMD[rRD_] <= wDDAT;
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rMEMD[rRD_] <= wDDAT;
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end
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end
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3'o1: xDWBDAT <= {(2){wREGD[15:0]}};
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3'o1: xDWBDAT <= {(2){wREGD[15:0]}};
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3'o5: xDWBDAT <= {(2){rRESULT[15:0]}};
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3'o5: xDWBDAT <= {(2){rRESULT[15:0]}};
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// 32-bit
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// 32-bit
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3'o2, 3'o3: xDWBDAT <= wREGD;
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3'o2, 3'o3: xDWBDAT <= wREGD;
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3'o6, 3'o7: xDWBDAT <= rRESULT;
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3'o6, 3'o7: xDWBDAT <= rRESULT;
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endcase // case (rOPC[1:0])
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endcase // case ({fDFWD,rOPC[1:0]})
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always @(/*AUTOSENSE*/rDWBSEL or wDWBDAT)
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always @(/*AUTOSENSE*/rDWBSEL or wDWBDAT)
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case (rDWBSEL)
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case (rDWBSEL)
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// 8-bit
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// 8-bit
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4'h8: sDWBDAT <= {24'd0,wDWBDAT[31:24]};
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4'h8: sDWBDAT <= {24'd0,wDWBDAT[31:24]};
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default: sDWBDAT <= wDWBDAT;
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default: sDWBDAT <= wDWBDAT;
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endcase // case (rDWBSEL)
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endcase // case (rDWBSEL)
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// PIPELINE REGISTERS //////////////////////////////////////////////////
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// PIPELINE REGISTERS //////////////////////////////////////////////////
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always @(negedge nclk or negedge nrst)
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always @(negedge nclk)
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if (!nrst) begin
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if (prst) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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rDWBDAT <= 32'h0;
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rDWBDAT <= 32'h0;
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rPC_ <= 30'h0;
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rPC_ <= 30'h0;
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rRD_ <= 5'h0;
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rRD_ <= 5'h0;
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// End of automatics
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// End of automatics
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end else if (nrun) begin
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end else if (prun) begin
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rDWBDAT <= #1 xDWBDAT;
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rDWBDAT <= #1 xDWBDAT;
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rPC_ <= xPC_;
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rPC_ <= xPC_;
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rRD_ <= xRD_;
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rRD_ <= xRD_;
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end
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end
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