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// Last Modified On: 2006-12-29
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// Last Modified On: 2006-12-29
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// Update Count : 0
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// Update Count : 0
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// Status : Unknown, Use with caution!
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// Status : Unknown, Use with caution!
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/*
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/*
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* $Id: aeMB_regfile.v,v 1.1 2007-03-09 17:52:17 sybreon Exp $
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* $Id: aeMB_regfile.v,v 1.2 2007-03-26 12:21:31 sybreon Exp $
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*
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*
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* Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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* Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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*
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*
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* This library is free software; you can redistribute it and/or modify it
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* This library is free software; you can redistribute it and/or modify it
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* under the terms of the GNU Lesser General Public License as published by
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* under the terms of the GNU Lesser General Public License as published by
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* special actions during hardware exception/interrupts. Data forwarding
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* special actions during hardware exception/interrupts. Data forwarding
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* is also taken care of inside here to simplify decode logic.
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* is also taken care of inside here to simplify decode logic.
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*
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*
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* HISTORY
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* HISTORY
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* $Log: not supported by cvs2svn $
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* $Log: not supported by cvs2svn $
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* Revision 1.1 2007/03/09 17:52:17 sybreon
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* initial import
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*
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*
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*
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*/
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*/
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module aeMB_regfile(/*AUTOARG*/
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module aeMB_regfile(/*AUTOARG*/
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// Outputs
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// Outputs
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reg [31:0] r08,r09,r0A,r0B,r0C,r0D,r0E,r0F;
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reg [31:0] r08,r09,r0A,r0B,r0C,r0D,r0E,r0F;
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reg [31:0] r10,r11,r12,r13,r14,r15,r16,r17;
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reg [31:0] r10,r11,r12,r13,r14,r15,r16,r17;
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reg [31:0] r18,r19,r1A,r1B,r1C,r1D,r1E,r1F;
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reg [31:0] r18,r19,r1A,r1B,r1C,r1D,r1E,r1F;
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// FLAGS
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// FLAGS
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wire fWE = rRWE;
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wire fWE = rRWE & ~rDWBWE;
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wire fLNK = rLNK;
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wire fLNK = rLNK;
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wire fLD = rDWBSTB ^ rDWBWE;
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wire fLD = rDWBSTB ^ rDWBWE;
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// PC Latch
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// PC Latch
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reg [31:0] rPC_;
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reg [31:0] rPC_;
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end else begin // if (drun)
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end else begin // if (drun)
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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rDWBDAT <= 32'h0;
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rDWBDAT <= 32'h0;
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// End of automatics
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// End of automatics
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end
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end // else: !if(drun)
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// Load Registers
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// Load Registers
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reg [31:0] rREGA, rREGB;
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reg [31:0] rREGA, rREGB;
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always @(posedge nclk or negedge nrst)
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always @(posedge nclk or negedge nrst)
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if (!nrst) begin
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if (!nrst) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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rREGA <= 32'h0;
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rREGA <= 32'h0;
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rREGB <= 32'h0;
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rREGB <= 32'h0;
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// End of automatics
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// End of automatics
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end
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end // else: !if(drun)
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// Normal Registers
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// Normal Registers
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wire fR00 = (rRD_ == 5'h00);
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wire fR00 = (rRD_ == 5'h00);
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wire fR01 = (rRD_ == 5'h01);
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wire fR01 = (rRD_ == 5'h01);
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r1C <= #1 (fR1C & fLD) ? wDWBDAT : (fR1C & fLNK) ? rPC_ : (fR1C & fWE) ? rRESULT : r1C;
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r1C <= #1 (fR1C & fLD) ? wDWBDAT : (fR1C & fLNK) ? rPC_ : (fR1C & fWE) ? rRESULT : r1C;
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r1D <= #1 (fR1D & fLD) ? wDWBDAT : (fR1D & fLNK) ? rPC_ : (fR1D & fWE) ? rRESULT : r1D;
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r1D <= #1 (fR1D & fLD) ? wDWBDAT : (fR1D & fLNK) ? rPC_ : (fR1D & fWE) ? rRESULT : r1D;
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r1E <= #1 (fR1E & fLD) ? wDWBDAT : (fR1E & fLNK) ? rPC_ : (fR1E & fWE) ? rRESULT : r1E;
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r1E <= #1 (fR1E & fLD) ? wDWBDAT : (fR1E & fLNK) ? rPC_ : (fR1E & fWE) ? rRESULT : r1E;
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r1F <= #1 (fR1F & fLD) ? wDWBDAT : (fR1F & fLNK) ? rPC_ : (fR1F & fWE) ? rRESULT : r1F;
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r1F <= #1 (fR1F & fLD) ? wDWBDAT : (fR1F & fLNK) ? rPC_ : (fR1F & fWE) ? rRESULT : r1F;
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*/
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*/
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end // if (drun)
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end // else: !if(!nrst)
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// Special Registers
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// Special Registers
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always @(negedge nclk or negedge nrst)
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always @(negedge nclk or negedge nrst)
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if (!nrst) begin
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if (!nrst) begin
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/*AUTORESET*/
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/*AUTORESET*/
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r0E <= #1 (rFSM == 2'b11) ? rPC : // Needs verification
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r0E <= #1 (rFSM == 2'b11) ? rPC : // Needs verification
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(!fR0E) ? r0E : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ? rRESULT : r0E;
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(!fR0E) ? r0E : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ? rRESULT : r0E;
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// R11 - Exception
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// R11 - Exception
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r11 <= #1 (rFSM == 2'b10) ? rPC : // Needs verification
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r11 <= #1 (rFSM == 2'b10) ? rPC : // Needs verification
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(!fR11) ? r11 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ? rRESULT : r11;
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(!fR11) ? r11 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ? rRESULT : r11;
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end
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end // else: !if(!nrst)
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endmodule // aeMB_regfile
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endmodule // aeMB_regfile
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// Local Variables:
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// Local Variables:
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