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// Last Modified On: 2006-12-29
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// Last Modified On: 2006-12-29
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// Update Count : 0
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// Update Count : 0
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// Status : Unknown, Use with caution!
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// Status : Unknown, Use with caution!
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/*
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/*
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* $Id: aeMB_regfile.v,v 1.2 2007-03-26 12:21:31 sybreon Exp $
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* $Id: aeMB_regfile.v,v 1.3 2007-04-03 14:46:26 sybreon Exp $
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*
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*
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* Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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* Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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*
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*
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* This library is free software; you can redistribute it and/or modify it
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* This library is free software; you can redistribute it and/or modify it
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* under the terms of the GNU Lesser General Public License as published by
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* under the terms of the GNU Lesser General Public License as published by
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* special actions during hardware exception/interrupts. Data forwarding
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* special actions during hardware exception/interrupts. Data forwarding
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* is also taken care of inside here to simplify decode logic.
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* is also taken care of inside here to simplify decode logic.
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*
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*
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* HISTORY
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* HISTORY
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* $Log: not supported by cvs2svn $
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* $Log: not supported by cvs2svn $
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* Revision 1.2 2007/03/26 12:21:31 sybreon
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* Fixed a minor bug where RD is trashed by a STORE instruction. Spotted by Joon Lee.
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*
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* Revision 1.1 2007/03/09 17:52:17 sybreon
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* Revision 1.1 2007/03/09 17:52:17 sybreon
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* initial import
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* initial import
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*
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*
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*
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*
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*/
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*/
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end else begin
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end else begin
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rPC_ <= #1 rPC;
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rPC_ <= #1 rPC;
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end
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end
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// DWB data - Endian Correction
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// DWB data - Endian Correction
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wire [31:0] wDWBDAT = dwb_dat_i;
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reg [31:0] rDWBDAT;
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reg [31:0] rDWBDAT;
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wire fDFWD = (rRD == rRD_) & fWE;
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wire fDFWD = (rRD == rRD_) & fWE;
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assign dwb_dat_o = rDWBDAT;
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//assign dwb_dat_o = rDWBDAT;
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//wire [31:0] wDWBDAT = dwb_dat_i;
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assign dwb_dat_o = {rDWBDAT[7:0],rDWBDAT[15:8],rDWBDAT[23:16],rDWBDAT[31:24]};
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wire [31:0] wDWBDAT = {dwb_dat_i[7:0],dwb_dat_i[15:8],dwb_dat_i[23:16],dwb_dat_i[31:24]};
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always @(negedge nclk or negedge nrst)
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always @(negedge nclk or negedge nrst)
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if (!nrst) begin
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if (!nrst) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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r11 <= #1 (rFSM == 2'b10) ? rPC : // Needs verification
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r11 <= #1 (rFSM == 2'b10) ? rPC : // Needs verification
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(!fR11) ? r11 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ? rRESULT : r11;
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(!fR11) ? r11 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ? rRESULT : r11;
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end // else: !if(!nrst)
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end // else: !if(!nrst)
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// Simulation ONLY
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always @(negedge nclk) begin
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if ((fWE & (rRD_== 5'd0)) || (fLNK & (rRD_== 5'd0)) || (fLD & (rRD_== 5'd0))) $displayh("!!! Warning: Write to R0.");
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end
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endmodule // aeMB_regfile
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endmodule // aeMB_regfile
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// Local Variables:
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// Local Variables:
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// verilog-library-directories:(".")
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// verilog-library-directories:(".")
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// verilog-library-files:("")
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// verilog-library-files:("")
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