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// -*- Mode: Verilog -*-
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// -*- Mode: Verilog -*-
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// Filename : aeMB_regfile.v
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// Filename : aeMB_regfile.v
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// Description : AEMB Register File
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// Description : AEMB Register File
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// Author : Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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// Author : Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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// Created On : Fri Dec 29 16:17:31 2006
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// Created On : Fri Dec 29 16:17:31 2006
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// Last Modified By: Shawn Tan
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// Last Modified By: $Author: sybreon $
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// Last Modified On: 2006-12-29
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// Last Modified On: $Date: 2007-04-04 06:11:47 $
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// Update Count : 0
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// Update Count : $Revision: 1.4 $
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// Status : Unknown, Use with caution!
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// Status : $State: Exp $
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/*
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/*
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* $Id: aeMB_regfile.v,v 1.3 2007-04-03 14:46:26 sybreon Exp $
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* $Id: aeMB_regfile.v,v 1.4 2007-04-04 06:11:47 sybreon Exp $
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*
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*
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* AEMB Register File
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* Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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* Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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*
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*
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* This library is free software; you can redistribute it and/or modify it
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* This library is free software; you can redistribute it and/or modify it
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* under the terms of the GNU Lesser General Public License as published by
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* under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation; either version 2.1 of the License,
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* the Free Software Foundation; either version 2.1 of the License,
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* special actions during hardware exception/interrupts. Data forwarding
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* special actions during hardware exception/interrupts. Data forwarding
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* is also taken care of inside here to simplify decode logic.
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* is also taken care of inside here to simplify decode logic.
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*
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*
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* HISTORY
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* HISTORY
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* $Log: not supported by cvs2svn $
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* $Log: not supported by cvs2svn $
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* Revision 1.3 2007/04/03 14:46:26 sybreon
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* Fixed endian correction issues on data bus.
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*
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* Revision 1.2 2007/03/26 12:21:31 sybreon
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* Revision 1.2 2007/03/26 12:21:31 sybreon
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* Fixed a minor bug where RD is trashed by a STORE instruction. Spotted by Joon Lee.
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* Fixed a minor bug where RD is trashed by a STORE instruction. Spotted by Joon Lee.
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*
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*
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* Revision 1.1 2007/03/09 17:52:17 sybreon
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* Revision 1.1 2007/03/09 17:52:17 sybreon
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* initial import
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* initial import
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*
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*
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*
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*/
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*/
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module aeMB_regfile(/*AUTOARG*/
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module aeMB_regfile(/*AUTOARG*/
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// Outputs
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// Outputs
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dwb_dat_o, rREGA, rREGB,
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dwb_dat_o, rREGA, rREGB,
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rPC_ <= #1 rPC;
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rPC_ <= #1 rPC;
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end
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end
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// DWB data - Endian Correction
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// DWB data - Endian Correction
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reg [31:0] rDWBDAT;
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reg [31:0] rDWBDAT;
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wire fDFWD = (rRD == rRD_) & fWE;
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//assign dwb_dat_o = rDWBDAT;
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//assign dwb_dat_o = rDWBDAT;
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//wire [31:0] wDWBDAT = dwb_dat_i;
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//wire [31:0] wDWBDAT = dwb_dat_i;
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assign dwb_dat_o = {rDWBDAT[7:0],rDWBDAT[15:8],rDWBDAT[23:16],rDWBDAT[31:24]};
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assign dwb_dat_o = {rDWBDAT[7:0],rDWBDAT[15:8],rDWBDAT[23:16],rDWBDAT[31:24]};
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wire [31:0] wDWBDAT = {dwb_dat_i[7:0],dwb_dat_i[15:8],dwb_dat_i[23:16],dwb_dat_i[31:24]};
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wire [31:0] wDWBDAT = {dwb_dat_i[7:0],dwb_dat_i[15:8],dwb_dat_i[23:16],dwb_dat_i[31:24]};
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// Forwarding Control
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wire fDFWD = (rRD == rRD_) & fWE;
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wire fMFWD = rDWBSTB & ~rDWBWE;
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wire [31:0] wRESULT = (fMFWD) ? wDWBDAT : rRESULT;
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// Register Load
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always @(negedge nclk or negedge nrst)
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always @(negedge nclk or negedge nrst)
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if (!nrst) begin
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if (!nrst) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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rDWBDAT <= 32'h0;
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rDWBDAT <= 32'h0;
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// End of automatics
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// End of automatics
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end else if (drun) begin
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end else if (drun) begin
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case (rRD)
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case (rRD)
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5'h00: rDWBDAT <= #1 (fDFWD) ? rRESULT : r00;
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5'h00: rDWBDAT <= #1 (fDFWD) ? wRESULT : r00;
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5'h01: rDWBDAT <= #1 (fDFWD) ? rRESULT : r01;
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5'h01: rDWBDAT <= #1 (fDFWD) ? wRESULT : r01;
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5'h02: rDWBDAT <= #1 (fDFWD) ? rRESULT : r02;
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5'h02: rDWBDAT <= #1 (fDFWD) ? wRESULT : r02;
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5'h03: rDWBDAT <= #1 (fDFWD) ? rRESULT : r03;
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5'h03: rDWBDAT <= #1 (fDFWD) ? wRESULT : r03;
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5'h04: rDWBDAT <= #1 (fDFWD) ? rRESULT : r04;
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5'h04: rDWBDAT <= #1 (fDFWD) ? wRESULT : r04;
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5'h05: rDWBDAT <= #1 (fDFWD) ? rRESULT : r05;
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5'h05: rDWBDAT <= #1 (fDFWD) ? wRESULT : r05;
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5'h06: rDWBDAT <= #1 (fDFWD) ? rRESULT : r06;
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5'h06: rDWBDAT <= #1 (fDFWD) ? wRESULT : r06;
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5'h07: rDWBDAT <= #1 (fDFWD) ? rRESULT : r07;
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5'h07: rDWBDAT <= #1 (fDFWD) ? wRESULT : r07;
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5'h08: rDWBDAT <= #1 (fDFWD) ? rRESULT : r08;
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5'h08: rDWBDAT <= #1 (fDFWD) ? wRESULT : r08;
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5'h09: rDWBDAT <= #1 (fDFWD) ? rRESULT : r09;
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5'h09: rDWBDAT <= #1 (fDFWD) ? wRESULT : r09;
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5'h0A: rDWBDAT <= #1 (fDFWD) ? rRESULT : r0A;
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5'h0A: rDWBDAT <= #1 (fDFWD) ? wRESULT : r0A;
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5'h0B: rDWBDAT <= #1 (fDFWD) ? rRESULT : r0B;
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5'h0B: rDWBDAT <= #1 (fDFWD) ? wRESULT : r0B;
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5'h0C: rDWBDAT <= #1 (fDFWD) ? rRESULT : r0C;
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5'h0C: rDWBDAT <= #1 (fDFWD) ? wRESULT : r0C;
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5'h0D: rDWBDAT <= #1 (fDFWD) ? rRESULT : r0D;
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5'h0D: rDWBDAT <= #1 (fDFWD) ? wRESULT : r0D;
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5'h0E: rDWBDAT <= #1 (fDFWD) ? rRESULT : r0E;
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5'h0E: rDWBDAT <= #1 (fDFWD) ? wRESULT : r0E;
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5'h0F: rDWBDAT <= #1 (fDFWD) ? rRESULT : r0F;
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5'h0F: rDWBDAT <= #1 (fDFWD) ? wRESULT : r0F;
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5'h10: rDWBDAT <= #1 (fDFWD) ? rRESULT : r10;
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5'h10: rDWBDAT <= #1 (fDFWD) ? wRESULT : r10;
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5'h11: rDWBDAT <= #1 (fDFWD) ? rRESULT : r11;
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5'h11: rDWBDAT <= #1 (fDFWD) ? wRESULT : r11;
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5'h12: rDWBDAT <= #1 (fDFWD) ? rRESULT : r12;
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5'h12: rDWBDAT <= #1 (fDFWD) ? wRESULT : r12;
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5'h13: rDWBDAT <= #1 (fDFWD) ? rRESULT : r13;
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5'h13: rDWBDAT <= #1 (fDFWD) ? wRESULT : r13;
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5'h14: rDWBDAT <= #1 (fDFWD) ? rRESULT : r14;
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5'h14: rDWBDAT <= #1 (fDFWD) ? wRESULT : r14;
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5'h15: rDWBDAT <= #1 (fDFWD) ? rRESULT : r15;
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5'h15: rDWBDAT <= #1 (fDFWD) ? wRESULT : r15;
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5'h16: rDWBDAT <= #1 (fDFWD) ? rRESULT : r16;
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5'h16: rDWBDAT <= #1 (fDFWD) ? wRESULT : r16;
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5'h17: rDWBDAT <= #1 (fDFWD) ? rRESULT : r17;
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5'h17: rDWBDAT <= #1 (fDFWD) ? wRESULT : r17;
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5'h18: rDWBDAT <= #1 (fDFWD) ? rRESULT : r18;
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5'h18: rDWBDAT <= #1 (fDFWD) ? wRESULT : r18;
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5'h19: rDWBDAT <= #1 (fDFWD) ? rRESULT : r19;
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5'h19: rDWBDAT <= #1 (fDFWD) ? wRESULT : r19;
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5'h1A: rDWBDAT <= #1 (fDFWD) ? rRESULT : r1A;
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5'h1A: rDWBDAT <= #1 (fDFWD) ? wRESULT : r1A;
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5'h1B: rDWBDAT <= #1 (fDFWD) ? rRESULT : r1B;
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5'h1B: rDWBDAT <= #1 (fDFWD) ? wRESULT : r1B;
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5'h1C: rDWBDAT <= #1 (fDFWD) ? rRESULT : r1C;
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5'h1C: rDWBDAT <= #1 (fDFWD) ? wRESULT : r1C;
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5'h1D: rDWBDAT <= #1 (fDFWD) ? rRESULT : r1D;
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5'h1D: rDWBDAT <= #1 (fDFWD) ? wRESULT : r1D;
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5'h1E: rDWBDAT <= #1 (fDFWD) ? rRESULT : r1E;
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5'h1E: rDWBDAT <= #1 (fDFWD) ? wRESULT : r1E;
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5'h1F: rDWBDAT <= #1 (fDFWD) ? rRESULT : r1F;
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5'h1F: rDWBDAT <= #1 (fDFWD) ? wRESULT : r1F;
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endcase // case (rRD)
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endcase // case (rRD)
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end else begin // if (drun)
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end else begin // if (drun)
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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rDWBDAT <= 32'h0;
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rDWBDAT <= 32'h0;
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