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/* $Id: aeMB2_ctrl.v,v 1.3 2008-04-26 01:09:05 sybreon Exp $
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/* $Id: aeMB2_ctrl.v,v 1.4 2008-04-26 17:57:43 sybreon Exp $
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**
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**
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** AEMB2 EDK 6.2 COMPATIBLE CORE
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** AEMB2 EDK 6.2 COMPATIBLE CORE
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** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
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** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
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**
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**
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** This file is part of AEMB.
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** This file is part of AEMB.
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// control signals
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// control signals
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wire [31:0] wXCEOP = 32'hBA2D0020; // Vector 0x20
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wire [31:0] wXCEOP = 32'hBA2D0020; // Vector 0x20
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wire [31:0] wINTOP = 32'hB9CE0010; // Vector 0x10
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wire [31:0] wINTOP = 32'hB9CE0010; // Vector 0x10
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wire [31:0] wNOPOP = 32'h88000000; // branch-no-delay/stall
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wire [31:0] wNOPOP = 32'h88000000; // branch-no-delay/stall
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localparam [2:0] MUX_ALU = 3'o7,
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localparam [2:0] MUX_SFR = 3'o7,
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MUX_SFR = 3'o5,
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MUX_BSF = 3'o6,
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MUX_BSF = 3'o4,
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MUX_MUL = 3'o5,
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MUX_MUL = 3'o3,
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MUX_MEM = 3'o4,
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MUX_MEM = 3'o2,
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MUX_RPC = 3'o1,
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MUX_RPC = 3'o2,
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MUX_ALU = 3'o1,
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MUX_NOP = 3'o0;
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MUX_NOP = 3'o0;
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always @(posedge gclk)
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always @(posedge gclk)
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if (grst) begin
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if (grst) begin
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/*AUTORESET*/
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/*AUTORESET*/
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(hzd_bpc | hzd_fwd) ? 6'o42 :
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(hzd_bpc | hzd_fwd) ? 6'o42 :
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wOPC;
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wOPC;
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rd_of <= #1 wRD;
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rd_of <= #1 wRD;
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ra_of <= #1 wRA;
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ra_of <= #1 wRA;
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//rb_of <= #1 wRB;
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imm_of <= #1 wIMM;
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imm_of <= #1 wIMM;
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end // if (dena)
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end // if (dena)
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// immediate implementation
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// immediate implementation
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reg [15:0] rIMM0, rIMM1;
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reg [15:0] rIMM0, rIMM1;
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reg rFIM0, rFIM1;
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reg rFIM0, rFIM1;
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wire wFIMH = (gpha & AEMB_HTX[0]) ? rFIM1 : rFIM0;
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//wire wFIMH = (gpha & AEMB_HTX[0]) ? rFIM1 : rFIM0;
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wire [15:0] wIMMH = (gpha & AEMB_HTX[0]) ? rIMM1 : rIMM0;
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//wire [15:0] wIMMH = (gpha & AEMB_HTX[0]) ? rIMM1 : rIMM0;
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assign imm_if[15:0] = wIMM;
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assign imm_if[15:0] = wIMM;
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assign imm_if[31:16] = (wFIMH) ? wIMMH :
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assign imm_if[31:16] = (rFIM1) ? rIMM1 :
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{(16){wIMM[15]}};
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{(16){wIMM[15]}};
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// BARREL IMM
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always @(posedge gclk)
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always @(posedge gclk)
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if (grst) begin
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if (grst) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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rFIM0 <= 1'h0;
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rFIM0 <= 1'h0;
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rFIM1 <= 1'h0;
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rFIM1 <= 1'h0;
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rIMM0 <= 16'h0;
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rIMM0 <= 16'h0;
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rIMM1 <= 16'h0;
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rIMM1 <= 16'h0;
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// End of automatics
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// End of automatics
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end else if (dena) begin
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end else if (dena) begin
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if (gpha) begin
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rFIM1 <= #1 rFIM0;
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rFIM1 <= #1 fIMM & !hzd_bpc;
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rIMM1 <= #1 wIMM;
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end else begin
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rFIM0 <= #1 fIMM & !hzd_bpc;
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rFIM0 <= #1 fIMM & !hzd_bpc;
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rIMM1 <= #1 rIMM0;
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rIMM0 <= #1 wIMM;
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rIMM0 <= #1 wIMM;
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end
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end
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end
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// operand latch
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// operand latch
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reg wrb_ex;
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reg wrb_ex;
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reg fwd_ex;
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reg fwd_ex;
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reg [2:0] mux_mx;
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wire opb_fwd, opa_fwd, opd_fwd;
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wire opb_fwd, opa_fwd, opd_fwd;
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assign mux_opb = {wOPC[3], opb_fwd};
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assign mux_opb = {wOPC[3], opb_fwd};
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assign opb_fwd = (wRB == rd_ex) &
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assign opb_fwd = ~|(wRB ^ rd_ex) & // RB forwarding needed
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fwd_ex & wrb_ex;
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fwd_ex & wrb_ex;
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assign mux_opa = {(fBRU|fBCC), opa_fwd};
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assign mux_opa = {(fBRU|fBCC), opa_fwd};
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assign opa_fwd = (wRA == rd_ex) &
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assign opa_fwd = ~|(wRA ^ rd_ex) & // RA forwarding needed
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fwd_ex & wrb_ex;
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fwd_ex & wrb_ex;
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assign mux_opd = {fBCC, opd_fwd};
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assign mux_opd = {fBCC, opd_fwd};
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assign opd_fwd = (((wRA == rd_ex) & fBCC) |
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assign opd_fwd = (( ~|(wRA ^ rd_ex) & fBCC) |
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((wRD == rd_ex) & fSTR)) &
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( ~|(wRD ^ rd_ex) & fSTR)) &
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fwd_ex & wrb_ex;
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fwd_ex & wrb_ex;
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reg [2:0] mux_mx;
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always @(posedge gclk)
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always @(posedge gclk)
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if (grst) begin
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if (grst) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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fwd_ex <= 1'h0;
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fwd_ex <= 1'h0;
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mux_mx <= #1 mux_ex;
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mux_mx <= #1 mux_ex;
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mux_ex <= #1 mux_of;
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mux_ex <= #1 mux_of;
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rd_ex <= #1 rd_of;
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rd_ex <= #1 rd_of;
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end
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end
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always @(posedge gclk)
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always @(posedge gclk)
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if (grst) begin
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if (grst) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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opa_of <= 32'h0;
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opa_of <= 32'h0;
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case (mux_opb)
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case (mux_opb)
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2'o0: opb_of <= #1 opb_if;
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2'o0: opb_of <= #1 opb_if;
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2'o1: opb_of <= #1 alu_ex;
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2'o1: opb_of <= #1 alu_ex;
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2'o2: opb_of <= #1 imm_if;
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2'o2: opb_of <= #1 imm_if;
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2'o3: opb_of <= #1 imm_if;
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2'o3: opb_of <= #1 imm_if;
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//default: 32'hX;
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endcase // case (mux_opb)
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endcase // case (mux_opb)
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case (mux_opa)
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case (mux_opa)
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2'o0: opa_of <= #1 opa_if;
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2'o0: opa_of <= #1 opa_if;
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2'o1: opa_of <= #1 alu_ex;
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2'o1: opa_of <= #1 alu_ex;
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wire wFMUL = (mux_ex == MUX_MUL);
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wire wFMUL = (mux_ex == MUX_MUL);
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wire wFBSF = (mux_ex == MUX_BSF);
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wire wFBSF = (mux_ex == MUX_BSF);
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wire wFMEM = (mux_ex == MUX_MEM);
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wire wFMEM = (mux_ex == MUX_MEM);
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wire wFMOV = (mux_ex == MUX_SFR);
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wire wFMOV = (mux_ex == MUX_SFR);
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assign hzd_fwd = (opd_fwd | opa_fwd | opb_fwd) &
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assign hzd_fwd = (opd_fwd | opa_fwd | opb_fwd) & mux_ex[2];
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(wFMUL | wFBSF | wFMEM | wFMOV);
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//(wFMUL | wFBSF | wFMEM | wFMOV);
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assign hzd_bpc = (bra_ex[1] & !bra_ex[0]);
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assign hzd_bpc = (bra_ex[1] & !bra_ex[0]);
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endmodule // aeMB2_ctrl
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endmodule // aeMB2_ctrl
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/*
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/*
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$Log: not supported by cvs2svn $
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$Log: not supported by cvs2svn $
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Revision 1.3 2008/04/26 01:09:05 sybreon
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Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor.
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Revision 1.2 2008/04/20 16:34:32 sybreon
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Revision 1.2 2008/04/20 16:34:32 sybreon
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Basic version with some features left out.
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Basic version with some features left out.
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Revision 1.1 2008/04/18 00:21:52 sybreon
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Revision 1.1 2008/04/18 00:21:52 sybreon
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Initial import.
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Initial import.
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