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/* $Id: aeMB2_ctrl.v,v 1.4 2008-04-26 17:57:43 sybreon Exp $
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/* $Id: aeMB2_ctrl.v,v 1.5 2008-04-28 08:15:25 sybreon Exp $
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**
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**
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** AEMB2 EDK 6.2 COMPATIBLE CORE
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** AEMB2 EDK 6.2 COMPATIBLE CORE
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** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
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** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
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**
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**
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** This file is part of AEMB.
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** This file is part of AEMB.
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assign {wOPC, wRD, wRA, wIMM} = ich_dat;
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assign {wOPC, wRD, wRA, wIMM} = ich_dat;
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assign wRB = wIMM[15:11];
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assign wRB = wIMM[15:11];
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// decode main opgroups
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// decode main opgroups
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wire fSFT = (wOPC == 6'o44);
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//wire fSFT = (wOPC == 6'o44);
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wire fLOG = ({wOPC[5:4],wOPC[2]} == 3'o4);
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//wire fLOG = ({wOPC[5:4],wOPC[2]} == 3'o4);
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wire fMUL = (wOPC == 6'o20) | (wOPC == 6'o30);
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wire fMUL = (wOPC == 6'o20) | (wOPC == 6'o30);
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wire fBSF = (wOPC == 6'o21) | (wOPC == 6'o31);
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wire fBSF = (wOPC == 6'o21) | (wOPC == 6'o31);
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wire fDIV = (wOPC == 6'o22);
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//wire fDIV = (wOPC == 6'o22);
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wire fRTD = (wOPC == 6'o55);
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wire fRTD = (wOPC == 6'o55);
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wire fBCC = (wOPC == 6'o47) | (wOPC == 6'o57);
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wire fBCC = (wOPC == 6'o47) | (wOPC == 6'o57);
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wire fBRU = (wOPC == 6'o46) | (wOPC == 6'o56);
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wire fBRU = (wOPC == 6'o46) | (wOPC == 6'o56);
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wire fBRA = fBRU & wRA[3];
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//wire fBRA = fBRU & wRA[3];
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wire fIMM = (wOPC == 6'o54);
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wire fIMM = (wOPC == 6'o54);
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wire fMOV = (wOPC == 6'o45);
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wire fMOV = (wOPC == 6'o45);
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wire fLOD = ({wOPC[5:4],wOPC[2]} == 3'o6);
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wire fLOD = ({wOPC[5:4],wOPC[2]} == 3'o6);
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wire fSTR = ({wOPC[5:4],wOPC[2]} == 3'o7);
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wire fSTR = ({wOPC[5:4],wOPC[2]} == 3'o7);
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wire fLDST = (wOPC[5:4] == 2'o3);
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//wire fLDST = (wOPC[5:4] == 2'o3);
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wire fPUT = (wOPC == 6'o33) & wRB[4];
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//wire fPUT = (wOPC == 6'o33) & wRB[4];
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wire fGET = (wOPC == 6'o33) & !wRB[4];
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wire fGET = (wOPC == 6'o33) & !wRB[4];
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// control signals
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// control signals
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wire [31:0] wXCEOP = 32'hBA2D0020; // Vector 0x20
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//wire [31:0] wXCEOP = 32'hBA2D0020; // Vector 0x20
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wire [31:0] wINTOP = 32'hB9CE0010; // Vector 0x10
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//wire [31:0] wINTOP = 32'hB9CE0010; // Vector 0x10
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wire [31:0] wNOPOP = 32'h88000000; // branch-no-delay/stall
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//wire [31:0] wNOPOP = 32'h88000000; // branch-no-delay/stall
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localparam [2:0] MUX_SFR = 3'o7,
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localparam [2:0] MUX_SFR = 3'o7,
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MUX_BSF = 3'o6,
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MUX_BSF = 3'o6,
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MUX_MUL = 3'o5,
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MUX_MUL = 3'o5,
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MUX_MEM = 3'o4,
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MUX_MEM = 3'o4,
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rd_of <= 5'h0;
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rd_of <= 5'h0;
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// End of automatics
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// End of automatics
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end else if (dena) begin
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end else if (dena) begin
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mux_of <= #1
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mux_of <= #1
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(hzd_bpc | hzd_fwd) ? MUX_NOP :
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(hzd_bpc | hzd_fwd | fSTR | fRTD | fBCC) ? MUX_NOP :
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(fLOD | fGET) ? MUX_MEM :
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(fMOV) ? MUX_SFR :
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(fMOV) ? MUX_SFR :
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(fMUL) ? MUX_MUL :
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(fMUL) ? MUX_MUL :
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(fBSF) ? MUX_BSF :
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(fBSF) ? MUX_BSF :
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(fLOD | fGET) ? MUX_MEM :
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(fBRU) ? MUX_RPC :
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(fBRU) ? MUX_RPC :
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(fSTR | fRTD | fBCC) ? MUX_NOP :
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MUX_ALU;
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(|wRD) ? MUX_ALU :
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MUX_NOP;
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opc_of <= #1
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opc_of <= #1
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(hzd_bpc | hzd_fwd) ? 6'o42 :
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(hzd_bpc | hzd_fwd) ? 6'o42 : // XOR (SKIP)
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wOPC;
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wOPC;
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rd_of <= #1 wRD;
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rd_of <= #1 wRD;
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ra_of <= #1 wRA;
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ra_of <= #1 wRA;
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imm_of <= #1 wIMM;
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imm_of <= #1 wIMM;
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reg [2:0] mux_mx;
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reg [2:0] mux_mx;
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wire opb_fwd, opa_fwd, opd_fwd;
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wire opb_fwd, opa_fwd, opd_fwd;
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assign mux_opb = {wOPC[3], opb_fwd};
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assign mux_opb = {wOPC[3], opb_fwd};
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assign opb_fwd = ~|(wRB ^ rd_ex) & // RB forwarding needed
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assign opb_fwd = ((wRB ^ rd_ex) == 5'd0) & // RB forwarding needed
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fwd_ex & wrb_ex;
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fwd_ex & wrb_ex;
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assign mux_opa = {(fBRU|fBCC), opa_fwd};
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assign mux_opa = {(fBRU|fBCC), opa_fwd};
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assign opa_fwd = ~|(wRA ^ rd_ex) & // RA forwarding needed
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assign opa_fwd = ((wRA ^ rd_ex) == 5'd0) & // RA forwarding needed
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fwd_ex & wrb_ex;
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fwd_ex & wrb_ex;
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assign mux_opd = {fBCC, opd_fwd};
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assign mux_opd = {fBCC, opd_fwd};
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assign opd_fwd = (( ~|(wRA ^ rd_ex) & fBCC) |
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assign opd_fwd = (( ((wRA ^ rd_ex) == 5'd0) & fBCC) | // RA forwarding
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( ~|(wRD ^ rd_ex) & fSTR)) &
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( ((wRD ^ rd_ex) == 5'd0) & fSTR)) & // RD forwarding
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fwd_ex & wrb_ex;
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fwd_ex & wrb_ex;
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always @(posedge gclk)
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always @(posedge gclk)
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if (grst) begin
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if (grst) begin
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/*AUTORESET*/
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/*AUTORESET*/
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endcase // case (mux_opa)
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endcase // case (mux_opa)
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end // if (dena)
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end // if (dena)
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// Hazard Detection
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// Hazard Detection
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wire wFMUL = (mux_ex == MUX_MUL);
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//wire wFMUL = (mux_ex == MUX_MUL);
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wire wFBSF = (mux_ex == MUX_BSF);
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//wire wFBSF = (mux_ex == MUX_BSF);
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wire wFMEM = (mux_ex == MUX_MEM);
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//wire wFMEM = (mux_ex == MUX_MEM);
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wire wFMOV = (mux_ex == MUX_SFR);
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//wire wFMOV = (mux_ex == MUX_SFR);
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assign hzd_fwd = (opd_fwd | opa_fwd | opb_fwd) & mux_ex[2];
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assign hzd_fwd = (opd_fwd | opa_fwd | opb_fwd) & mux_ex[2];
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//(wFMUL | wFBSF | wFMEM | wFMOV);
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//(wFMUL | wFBSF | wFMEM | wFMOV);
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assign hzd_bpc = (bra_ex[1] & !bra_ex[0]);
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assign hzd_bpc = (bra_ex[1] & !bra_ex[0]);
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endmodule // aeMB2_ctrl
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endmodule // aeMB2_ctrl
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/*
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/*
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$Log: not supported by cvs2svn $
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$Log: not supported by cvs2svn $
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Revision 1.4 2008/04/26 17:57:43 sybreon
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Minor performance improvements.
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Revision 1.3 2008/04/26 01:09:05 sybreon
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Revision 1.3 2008/04/26 01:09:05 sybreon
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Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor.
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Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor.
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Revision 1.2 2008/04/20 16:34:32 sybreon
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Revision 1.2 2008/04/20 16:34:32 sybreon
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Basic version with some features left out.
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Basic version with some features left out.
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