| Line 1... |
Line 1... |
/* $Id: aeMB2_ctrl.v,v 1.5 2008-04-28 08:15:25 sybreon Exp $
|
/* $Id: aeMB2_ctrl.v,v 1.6 2008-05-01 08:32:58 sybreon Exp $
|
**
|
**
|
** AEMB2 EDK 6.2 COMPATIBLE CORE
|
** AEMB2 EDK 6.2 COMPATIBLE CORE
|
** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
|
** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
|
**
|
**
|
** This file is part of AEMB.
|
** This file is part of AEMB.
|
| Line 30... |
Line 30... |
module aeMB2_ctrl (/*AUTOARG*/
|
module aeMB2_ctrl (/*AUTOARG*/
|
// Outputs
|
// Outputs
|
opa_of, opb_of, opd_of, opc_of, ra_of, rd_of, imm_of, rd_ex,
|
opa_of, opb_of, opd_of, opc_of, ra_of, rd_of, imm_of, rd_ex,
|
mux_of, mux_ex, hzd_bpc, hzd_fwd,
|
mux_of, mux_ex, hzd_bpc, hzd_fwd,
|
// Inputs
|
// Inputs
|
opa_if, opb_if, opd_if, bra_ex, rpc_if, alu_ex, ich_dat, gclk,
|
opa_if, opb_if, opd_if, brk_if, bra_ex, rpc_if, alu_ex, ich_dat,
|
grst, dena, iena, gpha
|
gclk, grst, dena, iena, gpha
|
);
|
);
|
parameter AEMB_HTX = 1;
|
parameter AEMB_HTX = 1;
|
|
|
// EX CONTROL
|
// EX CONTROL
|
output [31:0] opa_of;
|
output [31:0] opa_of;
|
| Line 56... |
Line 56... |
// WB CONTROL
|
// WB CONTROL
|
output [2:0] mux_of,
|
output [2:0] mux_of,
|
mux_ex;
|
mux_ex;
|
|
|
// INTERNAL
|
// INTERNAL
|
|
input [1:0] brk_if;
|
input [1:0] bra_ex;
|
input [1:0] bra_ex;
|
input [31:2] rpc_if;
|
input [31:2] rpc_if;
|
input [31:0] alu_ex;
|
input [31:0] alu_ex;
|
input [31:0] ich_dat;
|
input [31:0] ich_dat;
|
|
|
| Line 85... |
Line 86... |
reg [4:0] ra_of;
|
reg [4:0] ra_of;
|
reg [4:0] rd_ex;
|
reg [4:0] rd_ex;
|
reg [4:0] rd_of;
|
reg [4:0] rd_of;
|
// End of automatics
|
// End of automatics
|
|
|
|
wire fINT;
|
|
//wire [31:0] wXCEOP = 32'hBA2D0020; // Vector 0x20
|
|
wire [31:0] wINTOP = 32'hB9CD0010; // Vector 0x10
|
|
//wire [31:0] wNOPOP = 32'h88000000; // branch-no-delay/stall
|
|
|
wire [1:0] mux_opa, mux_opb, mux_opd;
|
wire [1:0] mux_opa, mux_opb, mux_opd;
|
|
|
// translate signals
|
// translate signals
|
wire [4:0] wRD, wRA, wRB;
|
wire [4:0] wRD, wRA, wRB;
|
wire [5:0] wOPC;
|
wire [5:0] wOPC;
|
wire [15:0] wIMM;
|
wire [15:0] wIMM;
|
wire [31:0] imm_if;
|
wire [31:0] imm_if;
|
|
|
assign {wOPC, wRD, wRA, wIMM} = ich_dat;
|
assign {wOPC, wRD, wRA, wIMM} = (fINT) ? wINTOP : ich_dat;
|
assign wRB = wIMM[15:11];
|
assign wRB = wIMM[15:11];
|
|
|
// decode main opgroups
|
// decode main opgroups
|
|
|
//wire fSFT = (wOPC == 6'o44);
|
//wire fSFT = (wOPC == 6'o44);
|
| Line 117... |
Line 123... |
//wire fPUT = (wOPC == 6'o33) & wRB[4];
|
//wire fPUT = (wOPC == 6'o33) & wRB[4];
|
wire fGET = (wOPC == 6'o33) & !wRB[4];
|
wire fGET = (wOPC == 6'o33) & !wRB[4];
|
|
|
|
|
// control signals
|
// control signals
|
//wire [31:0] wXCEOP = 32'hBA2D0020; // Vector 0x20
|
|
//wire [31:0] wINTOP = 32'hB9CE0010; // Vector 0x10
|
|
//wire [31:0] wNOPOP = 32'h88000000; // branch-no-delay/stall
|
|
|
|
localparam [2:0] MUX_SFR = 3'o7,
|
localparam [2:0] MUX_SFR = 3'o7,
|
MUX_BSF = 3'o6,
|
MUX_BSF = 3'o6,
|
MUX_MUL = 3'o5,
|
MUX_MUL = 3'o5,
|
MUX_MEM = 3'o4,
|
MUX_MEM = 3'o4,
|
|
|
| Line 189... |
Line 191... |
|
|
rIMM1 <= #1 rIMM0;
|
rIMM1 <= #1 rIMM0;
|
rIMM0 <= #1 wIMM;
|
rIMM0 <= #1 wIMM;
|
end
|
end
|
|
|
|
assign fINT = brk_if[0] & !gpha & !rFIM1;
|
|
|
// operand latch
|
// operand latch
|
reg wrb_ex;
|
reg wrb_ex;
|
reg fwd_ex;
|
reg fwd_ex;
|
reg [2:0] mux_mx;
|
reg [2:0] mux_mx;
|
|
|
| Line 276... |
Line 280... |
|
|
endmodule // aeMB2_ctrl
|
endmodule // aeMB2_ctrl
|
|
|
/*
|
/*
|
$Log: not supported by cvs2svn $
|
$Log: not supported by cvs2svn $
|
|
Revision 1.5 2008/04/28 08:15:25 sybreon
|
|
Optimisations.
|
|
|
Revision 1.4 2008/04/26 17:57:43 sybreon
|
Revision 1.4 2008/04/26 17:57:43 sybreon
|
Minor performance improvements.
|
Minor performance improvements.
|
|
|
Revision 1.3 2008/04/26 01:09:05 sybreon
|
Revision 1.3 2008/04/26 01:09:05 sybreon
|
Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor.
|
Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor.
|
