URL
https://opencores.org/ocsvn/aemb/aemb/trunk
[/] [aemb/] [trunk/] [rtl/] [verilog/] [aeMB2_ctrl.v] - Diff between revs 157 and 160
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
Rev 157 |
Rev 160 |
Line 1... |
Line 1... |
/* $Id: aeMB2_ctrl.v,v 1.6 2008-05-01 08:32:58 sybreon Exp $
|
/* $Id: aeMB2_ctrl.v,v 1.7 2008-05-11 13:50:50 sybreon Exp $
|
**
|
**
|
** AEMB2 EDK 6.2 COMPATIBLE CORE
|
** AEMB2 EDK 6.2 COMPATIBLE CORE
|
** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
|
** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
|
**
|
**
|
** This file is part of AEMB.
|
** This file is part of AEMB.
|
Line 191... |
Line 191... |
|
|
rIMM1 <= #1 rIMM0;
|
rIMM1 <= #1 rIMM0;
|
rIMM0 <= #1 wIMM;
|
rIMM0 <= #1 wIMM;
|
end
|
end
|
|
|
assign fINT = brk_if[0] & !gpha & !rFIM1;
|
assign fINT = brk_if[0] & gpha & !rFIM1;
|
|
|
// operand latch
|
// operand latch
|
reg wrb_ex;
|
reg wrb_ex;
|
reg fwd_ex;
|
reg fwd_ex;
|
reg [2:0] mux_mx;
|
reg [2:0] mux_mx;
|
Line 280... |
Line 280... |
|
|
endmodule // aeMB2_ctrl
|
endmodule // aeMB2_ctrl
|
|
|
/*
|
/*
|
$Log: not supported by cvs2svn $
|
$Log: not supported by cvs2svn $
|
|
Revision 1.6 2008/05/01 08:32:58 sybreon
|
|
Added interrupt capability.
|
|
|
Revision 1.5 2008/04/28 08:15:25 sybreon
|
Revision 1.5 2008/04/28 08:15:25 sybreon
|
Optimisations.
|
Optimisations.
|
|
|
Revision 1.4 2008/04/26 17:57:43 sybreon
|
Revision 1.4 2008/04/26 17:57:43 sybreon
|
Minor performance improvements.
|
Minor performance improvements.
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.