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[/] [aemb/] [trunk/] [rtl/] [verilog/] [aeMB2_ctrl.v] - Diff between revs 206 and 207

Rev 206	Rev 207
Line 31...	Line 31...
`// Outputs`	`// Outputs`
`opa_of, opb_of, opd_of, opc_of, ra_of, rd_of, imm_of, rd_ex,`	`opa_of, opb_of, opd_of, opc_of, ra_of, rd_of, imm_of, rd_ex,`
`mux_of, mux_ex, hzd_bpc, hzd_fwd,`	`mux_of, mux_ex, hzd_bpc, hzd_fwd,`
`// Inputs`	`// Inputs`
`opa_if, opb_if, opd_if, brk_if, bra_ex, rpc_if, alu_ex, ich_dat,`	`opa_if, opb_if, opd_if, brk_if, bra_ex, rpc_if, alu_ex, ich_dat,`
`gclk, grst, dena, iena, gpha`	`exc_dwb, exc_ill, exc_iwb, gclk, grst, dena, iena, gpha`
`);`	`);`
`parameter AEMB_HTX = 1;`	`parameter AEMB_HTX = 1;`

`// EX CONTROL`	`// EX CONTROL`
`output [31:0] opa_of;`	`output [31:0] opa_of;`
Line 62...	Line 62...
`input [1:0] bra_ex;`	`input [1:0] bra_ex;`
`input [31:2] rpc_if;`	`input [31:2] rpc_if;`
`input [31:0] alu_ex;`	`input [31:0] alu_ex;`
`input [31:0] ich_dat;`	`input [31:0] ich_dat;`

	`input [1:0] exc_dwb;`
	`input exc_ill;`
	`input exc_iwb;`

`output hzd_bpc;`	`output hzd_bpc;`
`output hzd_fwd;`	`output hzd_fwd;`

`// SYSTEM`	`// SYSTEM`
`input gclk,`	`input gclk,`
Line 194...	Line 198...
`rIMM1 <= #1 rIMM0;`	`rIMM1 <= #1 rIMM0;`
`rIMM0 <= #1 wIMM;`	`rIMM0 <= #1 wIMM;`
`end`	`end`

`assign fINT = brk_if[0] & gpha & !rFIM1;`	`assign fINT = brk_if[0] & gpha & !rFIM1;`
`assign fXCE = brk_if[1];`	`//assign fXCE = brk_if[1];`
	`assign fXCE = \|{exc_ill, exc_iwb, exc_dwb};`
`// & ((gpha & !rFIM1) \| (!gpha & rFIM0));`	`// & ((gpha & !rFIM1) \| (!gpha & rFIM0));`

`// operand latch`	`// operand latch`
`reg wrb_ex;`	`reg wrb_ex;`
`reg fwd_ex;`	`reg fwd_ex;`