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/* $Id: aeMB2_dwbif.v,v 1.3 2008-04-21 12:11:38 sybreon Exp $
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/* $Id: aeMB2_dwbif.v,v 1.4 2008-04-23 14:18:52 sybreon Exp $
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**
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**
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** AEMB2 EDK 6.2 COMPATIBLE CORE
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** AEMB2 EDK 6.2 COMPATIBLE CORE
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** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
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** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
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**
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**
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** This file is part of AEMB.
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** This file is part of AEMB.
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wire [3:0] wSEL = {opc_of[1:0], wOFF};
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wire [3:0] wSEL = {opc_of[1:0], wOFF};
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// ENABLE FEEDBACK
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// ENABLE FEEDBACK
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assign dwb_fb = (dwb_stb_o ~^ dwb_ack_i);
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assign dwb_fb = (dwb_stb_o ~^ dwb_ack_i);
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// Independent on pipeline
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reg [31:0] dwb_lat;
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always @(posedge gclk)
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if (grst) begin
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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dwb_mx <= 32'h0;
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// End of automatics
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end else if (dwb_stb_o & dwb_ack_i) begin
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// LATCH READS
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dwb_mx <= #1 dwb_dat_i;
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end
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// DATA bus
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// DATA bus
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assign dwb_adr_o = mem_ex; // passthru
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assign dwb_adr_o = mem_ex; // passthru
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// STORE SIZER
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// STORE SIZER
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// TODO: Move the right words to the right place
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// TODO: Move the right words to the right place
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// dwb_mx latch the correct bytes
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// dwb_mx latch the correct bytes
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// depending on dwb_sel_o.
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// depending on dwb_sel_o.
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dwb_wre_o <= #1 opc_of[2]; // SXX
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dwb_wre_o <= #1 opc_of[2]; // SXX
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// FIXME: May clash during cache refills
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dwb_mx <= #1 (dwb_ack_i) ? dwb_dat_i : dwb_lat;
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case (wSEL)
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case (wSEL)
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// 32'bit
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// 32'bit
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4'h8: dwb_sel_o <= #1 4'hF;
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4'h8: dwb_sel_o <= #1 4'hF;
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// 16'bit
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// 16'bit
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4'h4: dwb_sel_o <= #1 4'hC;
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4'h4: dwb_sel_o <= #1 4'hC;
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// TODO: ILLEGAL
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// TODO: ILLEGAL
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default: dwb_sel_o <= #1 4'hX;
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default: dwb_sel_o <= #1 4'hX;
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endcase // case (wSEL)
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endcase // case (wSEL)
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end // if (dena)
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end // if (dena)
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// dislocate from pipeline
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// Independent on pipeline
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reg [31:0] dwb_lat;
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always @(posedge gclk)
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if (grst) begin
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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dwb_lat <= 32'h0;
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dwb_mx <= 32'h0;
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// End of automatics
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end else if (dwb_stb_o & dwb_ack_i) begin
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// LATCH READS
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dwb_lat <= #1 dwb_dat_i;
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end
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always @(posedge gclk)
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always @(posedge gclk)
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if (grst) begin
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if (grst) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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dwb_cyc_o <= 1'h0;
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dwb_cyc_o <= 1'h0;
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dwb_stb_o <= 1'h0;
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dwb_stb_o <= 1'h0;
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// End of automatics
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// End of automatics
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end else if (dwb_ack_i ~^ dwb_stb_o) begin
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end else if (dwb_fb) begin
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dwb_stb_o <= #1
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dwb_stb_o <= #1
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(dena) ? &opc_of[5:4] : // LXX/SSS
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(dena) ? &opc_of[5:4] : // LXX/SSS
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(dwb_stb_o & !dwb_ack_i); // LXX/SSS
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(dwb_stb_o & !dwb_ack_i); // LXX/SSS
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dwb_cyc_o <= #1
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dwb_cyc_o <= #1
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(dena) ? &opc_of[5:4] | msr_ex[0] :
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(dena) ? &opc_of[5:4] | msr_ex[0] :
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assign dwb_tag_o = msr_ex[7]; // MSR_DCE
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assign dwb_tag_o = msr_ex[7]; // MSR_DCE
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endmodule // aeMB2_memif
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endmodule // aeMB2_memif
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2008/04/21 12:11:38 sybreon
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// Passes arithmetic tests with single thread.
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//
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// Revision 1.2 2008/04/20 16:34:32 sybreon
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// Revision 1.2 2008/04/20 16:34:32 sybreon
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// Basic version with some features left out.
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// Basic version with some features left out.
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//
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//
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// Revision 1.1 2008/04/18 00:21:52 sybreon
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// Revision 1.1 2008/04/18 00:21:52 sybreon
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// Initial import.
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// Initial import.
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