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/* $Id: aeMB2_dwbif.v,v 1.5 2008-04-26 01:09:05 sybreon Exp $
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/* $Id: aeMB2_dwbif.v,v 1.6 2008-04-26 17:57:43 sybreon Exp $
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**
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**
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** AEMB2 EDK 6.2 COMPATIBLE CORE
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** AEMB2 EDK 6.2 COMPATIBLE CORE
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** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
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** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
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**
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**
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** This file is part of AEMB.
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** This file is part of AEMB.
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// dwb_mx latch the correct bytes
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// dwb_mx latch the correct bytes
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// depending on dwb_sel_o.
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// depending on dwb_sel_o.
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dwb_wre_o <= #1 opc_of[2]; // SXX
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dwb_wre_o <= #1 opc_of[2]; // SXX
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dwb_mx <= #1 (dwb_ack_i) ? dwb_dat_i : dwb_lat;
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dwb_mx <= #1 (dwb_ack_i) ? dwb_dat_i : dwb_lat; // Latch input
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case (wSEL)
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case (wSEL) // Latch output
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// 32'bit
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// 32'bit
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4'h8: dwb_sel_o <= #1 4'hF;
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4'h8: dwb_sel_o <= #1 4'hF;
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// 16'bit
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// 16'bit
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4'h4: dwb_sel_o <= #1 4'hC;
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4'h4: dwb_sel_o <= #1 4'hC;
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4'h6: dwb_sel_o <= #1 4'h3;
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4'h6: dwb_sel_o <= #1 4'h3;
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// 8'bit
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// 8'bit
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4'h0: dwb_sel_o <= #1 4'h8;
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4'h0: dwb_sel_o <= #1 4'h8;
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4'h1: dwb_sel_o <= #1 4'h4;
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4'h1: dwb_sel_o <= #1 4'h4;
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4'h2: dwb_sel_o <= #1 4'h2;
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4'h2: dwb_sel_o <= #1 4'h2;
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4'h3: dwb_sel_o <= #1 4'h1;
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4'h3: dwb_sel_o <= #1 4'h1;
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// XSL bus
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4'hC, 4'hD, 4'hE, 4'hF:
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dwb_sel_o <= #1 4'h0;
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// TODO: ILLEGAL
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// TODO: ILLEGAL
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default: dwb_sel_o <= #1 4'hX;
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default: dwb_sel_o <= #1 4'hX;
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endcase // case (wSEL)
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endcase // case (wSEL)
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end // if (dena)
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end // if (dena)
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endmodule // aeMB2_dwbif
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endmodule // aeMB2_dwbif
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/*
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/*
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$Log: not supported by cvs2svn $
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$Log: not supported by cvs2svn $
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Revision 1.5 2008/04/26 01:09:05 sybreon
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Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor.
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Revision 1.4 2008/04/23 14:18:52 sybreon
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Revision 1.4 2008/04/23 14:18:52 sybreon
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Fixed pipelined latching of data bug.
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Fixed pipelined latching of data bug.
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Revision 1.3 2008/04/21 12:11:38 sybreon
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Revision 1.3 2008/04/21 12:11:38 sybreon
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Passes arithmetic tests with single thread.
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Passes arithmetic tests with single thread.
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