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module aeMB2_dwbif (/*AUTOARG*/
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module aeMB2_dwbif (/*AUTOARG*/
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// Outputs
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// Outputs
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dwb_adr_o, dwb_sel_o, dwb_stb_o, dwb_cyc_o, dwb_tag_o, dwb_wre_o,
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dwb_adr_o, dwb_sel_o, dwb_stb_o, dwb_cyc_o, dwb_tag_o, dwb_wre_o,
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dwb_dat_o, dwb_fb, sel_mx, dwb_mx, exc_dwb,
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dwb_dat_o, dwb_fb, sel_mx, dwb_mx, exc_dwb,
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// Inputs
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// Inputs
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dwb_dat_i, dwb_ack_i, dwb_err_i, imm_of, opd_of, opc_of, opa_of,
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dwb_dat_i, dwb_ack_i, imm_of, opd_of, opc_of, opa_of,
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opb_of, msr_ex, mem_ex, sfr_mx, gclk, grst, dena, gpha
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opb_of, msr_ex, mem_ex, sfr_mx, gclk, grst, dena, gpha
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);
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);
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parameter AEMB_DWB = 32; ///< data bus address width
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parameter AEMB_DWB = 32; ///< data bus address width
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// DWB control signals
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// DWB control signals
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dwb_tag_o, // cache enable
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dwb_tag_o, // cache enable
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dwb_wre_o;
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dwb_wre_o;
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output [31:0] dwb_dat_o;
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output [31:0] dwb_dat_o;
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input [31:0] dwb_dat_i;
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input [31:0] dwb_dat_i;
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input dwb_ack_i;
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input dwb_ack_i;
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input dwb_err_i; // for bus error exception
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//input dwb_err_i; // for bus error exception
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// INTERNAL
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// INTERNAL
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output dwb_fb;
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output dwb_fb;
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output [3:0] sel_mx;
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output [3:0] sel_mx;
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output [31:0] dwb_mx;
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output [31:0] dwb_mx;
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wire [1:0] wOFF = (opa_of[1:0] + opb_of[1:0]); // small adder
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wire [1:0] wOFF = (opa_of[1:0] + opb_of[1:0]); // small adder
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wire [3:0] wSEL = {opc_of[1:0], wOFF}; // byte selector info
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wire [3:0] wSEL = {opc_of[1:0], wOFF}; // byte selector info
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assign dwb_fb = (dwb_stb_o ~^ dwb_ack_i); // feedback
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assign dwb_fb = (dwb_stb_o ~^ dwb_ack_i); // feedback
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assign dwb_adr_o = mem_ex; // data-bus passthru
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assign dwb_adr_o = mem_ex; // data-bus passthru
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assign exc_dwb = {dwb_exc, dwb_err_i}; // exception signal
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// TODO: enable dwb_err_i exception pass-thru
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assign exc_dwb = {dwb_exc, 1'b0};
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// STORE SIZER
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// STORE SIZER
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// TODO: Move the right words to the right place
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// TODO: Move the right words to the right place
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// TODO: Make this work with dwb_mx to for partial word loads.
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// TODO: Make this work with dwb_mx to for partial word loads.
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// TODO: ILLEGAL
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// TODO: ILLEGAL
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default: dwb_sel_o <= #1 4'hX;
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default: dwb_sel_o <= #1 4'hX;
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endcase // case (wSEL)
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endcase // case (wSEL)
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// exception checking
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// exception checking
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case (opc_of[1:0])
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dwb_exc <= #1 &opc_of[5:4] & // only for LD/ST commands
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2'o2: dwb_exc <= #1 |wOFF[1:0];
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((opc_of[0] & wOFF[0]) | // misaligned 16-bit
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2'o1: dwb_exc <= #1 wOFF[0];
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(opc_of[1] & |wOFF[1:0]) // misaligned 32-bit
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default: dwb_exc <= #1 1'b0;
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);
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endcase // case (opc_of[1:0])
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/*
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case (opc_of[1:0])
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2'o2: dwb_exc <= #1 |wOFF[1:0] & &opc_of[5:4];
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2'o1: dwb_exc <= #1 wOFF[0] & &opc_of[5:4];
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default: dwb_exc <= #1 1'b0;
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endcase // case (opc_of[1:0])
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*/
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end // if (dena)
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end // if (dena)
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// Independent of pipeline
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// Independent of pipeline
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