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module aeMB2_dwbif (/*AUTOARG*/
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module aeMB2_dwbif (/*AUTOARG*/
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// Outputs
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// Outputs
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dwb_adr_o, dwb_sel_o, dwb_stb_o, dwb_cyc_o, dwb_tag_o, dwb_wre_o,
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dwb_adr_o, dwb_sel_o, dwb_stb_o, dwb_cyc_o, dwb_tag_o, dwb_wre_o,
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dwb_dat_o, dwb_fb, sel_mx, dwb_mx, exc_dwb,
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dwb_dat_o, dwb_fb, sel_mx, dwb_mx, exc_dwb,
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// Inputs
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// Inputs
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dwb_dat_i, dwb_ack_i, imm_of, opd_of, opc_of, opa_of,
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dwb_dat_i, dwb_ack_i, imm_of, opd_of, opc_of, opa_of, opb_of,
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opb_of, msr_ex, mem_ex, sfr_mx, gclk, grst, dena, gpha
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msr_ex, mem_ex, sfr_mx, gclk, grst, dena, gpha
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);
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);
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parameter AEMB_DWB = 32; ///< data bus address width
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parameter AEMB_DWB = 32; ///< data bus address width
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// DWB control signals
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// DWB control signals
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output [AEMB_DWB-1:2] dwb_adr_o;
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output [AEMB_DWB-1:2] dwb_adr_o;
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grst,
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grst,
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dena,
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dena,
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gpha;
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gpha;
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/*AUTOREG*/
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/*AUTOREG*/
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reg [3:0] dwb_sel_o;
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// Beginning of automatic regs (for this module's undeclared outputs)
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reg dwb_stb_o, dwb_cyc_o, dwb_wre_o;
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reg dwb_cyc_o;
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reg [31:0] dwb_dat_o;
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reg [31:0] dwb_dat_o;
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reg [3:0] sel_mx;
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reg [31:0] dwb_mx;
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reg [31:0] dwb_mx;
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reg [3:0] dwb_sel_o;
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reg dwb_stb_o;
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reg dwb_wre_o;
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reg [3:0] sel_mx;
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// End of automatics
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reg dwb_exc;
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reg dwb_exc;
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wire [1:0] wOFF = (opa_of[1:0] + opb_of[1:0]); // small adder
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wire [1:0] wOFF = (opa_of[1:0] + opb_of[1:0]); // small adder
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wire [3:0] wSEL = {opc_of[1:0], wOFF}; // byte selector info
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wire [3:0] wSEL = {opc_of[1:0], wOFF}; // byte selector info
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