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[/] [aemb/] [trunk/] [rtl/] [verilog/] [aeMB2_edk62.v] - Diff between revs 132 and 134

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/* $Id: aeMB2_edk62.v,v 1.5 2008-04-26 01:11:30 sybreon Exp $
/* $Id: aeMB2_edk62.v,v 1.6 2008-04-26 17:57:43 sybreon Exp $
**
**
** AEMB2 EDK 6.2 COMPATIBLE CORE
** AEMB2 EDK 6.2 COMPATIBLE CORE
** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
**
**
** This file is part of AEMB.
** This file is part of AEMB.
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 * This implements an EDK 6.2 software compatible core. It implements
 * This implements an EDK 6.2 software compatible core. It implements
   all the software instructions except for division and cache writes.
   all the software instructions except for division and cache writes.
 
 
 */
 */
 
 
 
// 973@95
 
 
module aeMB2_edk62 (/*AUTOARG*/
module aeMB2_edk62 (/*AUTOARG*/
   // Outputs
   // Outputs
   xwb_wre_o, xwb_tag_o, xwb_stb_o, xwb_sel_o, xwb_dat_o, xwb_cyc_o,
   xwb_wre_o, xwb_tag_o, xwb_stb_o, xwb_sel_o, xwb_dat_o, xwb_cyc_o,
   xwb_adr_o, iwb_wre_o, iwb_stb_o, iwb_sel_o, iwb_cyc_o, iwb_adr_o,
   xwb_adr_o, iwb_wre_o, iwb_stb_o, iwb_sel_o, iwb_cyc_o, iwb_adr_o,
   dwb_wre_o, dwb_tag_o, dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_cyc_o,
   dwb_wre_o, dwb_tag_o, dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_cyc_o,
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   xwb_dat_i, xwb_ack_i, sys_rst_i, sys_ena_i, sys_clk_i, iwb_dat_i,
   xwb_dat_i, xwb_ack_i, sys_rst_i, sys_ena_i, sys_clk_i, iwb_dat_i,
   iwb_ack_i, dwb_dat_i, dwb_ack_i
   iwb_ack_i, dwb_dat_i, dwb_ack_i
   );
   );
   parameter AEMB_IWB = 32; ///< INST bus width
   parameter AEMB_IWB = 32; ///< INST bus width
   parameter AEMB_DWB = 32; ///< DATA bus width
   parameter AEMB_DWB = 32; ///< DATA bus width
   parameter AEMB_XWB = 3; ///< XSEL bus width
   parameter AEMB_XWB = 5; ///< XSEL bus width
 
 
   parameter AEMB_HTX = 1; ///< hardware thread extension
 
 
 
   parameter AEMB_ICH = 11; ///< instruction cache size
   parameter AEMB_ICH = 11; ///< instruction cache size
   parameter AEMB_IDX = 6; ///< cache index size
   parameter AEMB_IDX = 6; ///< cache index size
 
 
   parameter AEMB_BSF = 1; ///< implement barrel shift
   parameter AEMB_BSF = 1; ///< implement barrel shift
   parameter AEMB_MUL = 1; ///< implement multiplier
   parameter AEMB_MUL = 1; ///< implement multiplier
   parameter AEMB_XSL = 1; ///< implement XSL bus
   parameter AEMB_XSL = 1; ///< implement XSL bus
 
   parameter AEMB_HTX = 1; ///< hardware thread extension
 
 
   /*AUTOOUTPUT*/
   /*AUTOOUTPUT*/
   // Beginning of automatic outputs (from unused autoinst outputs)
   // Beginning of automatic outputs (from unused autoinst outputs)
   output [AEMB_DWB-1:2] dwb_adr_o;             // From memif0 of aeMB2_memif.v
   output [AEMB_DWB-1:2] dwb_adr_o;             // From memif0 of aeMB2_memif.v
   output               dwb_cyc_o;              // From memif0 of aeMB2_memif.v
   output               dwb_cyc_o;              // From memif0 of aeMB2_memif.v
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endmodule // aeMB2_edk62
endmodule // aeMB2_edk62
 
 
/*
/*
 $Log: not supported by cvs2svn $
 $Log: not supported by cvs2svn $
 
 Revision 1.5  2008/04/26 01:11:30  sybreon
 
 Fixed minor typos.
 
 
 Revision 1.4  2008/04/26 01:09:05  sybreon
 Revision 1.4  2008/04/26 01:09:05  sybreon
 Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor.
 Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor.
 
 
 Revision 1.3  2008/04/21 12:11:38  sybreon
 Revision 1.3  2008/04/21 12:11:38  sybreon
 Passes arithmetic tests with single thread.
 Passes arithmetic tests with single thread.

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