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/* $Id: aeMB2_edk62.v,v 1.6 2008-04-26 17:57:43 sybreon Exp $
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/* $Id: aeMB2_edk62.v,v 1.7 2008-04-27 19:52:46 sybreon Exp $
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**
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**
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** AEMB2 EDK 6.2 COMPATIBLE CORE
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** AEMB2 EDK 6.2 COMPATIBLE CORE
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** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
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** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
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**
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**
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** This file is part of AEMB.
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** This file is part of AEMB.
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// 973@95
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// 973@95
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module aeMB2_edk62 (/*AUTOARG*/
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module aeMB2_edk62 (/*AUTOARG*/
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// Outputs
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// Outputs
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xwb_wre_o, xwb_tag_o, xwb_stb_o, xwb_sel_o, xwb_dat_o, xwb_cyc_o,
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xwb_wre_o, xwb_tag_o, xwb_stb_o, xwb_sel_o, xwb_dat_o, xwb_cyc_o,
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xwb_adr_o, iwb_wre_o, iwb_stb_o, iwb_sel_o, iwb_cyc_o, iwb_adr_o,
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xwb_adr_o, iwb_wre_o, iwb_tag_o, iwb_stb_o, iwb_sel_o, iwb_cyc_o,
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dwb_wre_o, dwb_tag_o, dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_cyc_o,
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iwb_adr_o, dwb_wre_o, dwb_tag_o, dwb_stb_o, dwb_sel_o, dwb_dat_o,
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dwb_adr_o,
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dwb_cyc_o, dwb_adr_o,
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// Inputs
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// Inputs
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xwb_dat_i, xwb_ack_i, sys_rst_i, sys_ena_i, sys_clk_i, iwb_dat_i,
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xwb_dat_i, xwb_ack_i, sys_rst_i, sys_ena_i, sys_clk_i, iwb_dat_i,
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iwb_ack_i, dwb_dat_i, dwb_ack_i
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iwb_ack_i, dwb_dat_i, dwb_ack_i
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);
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);
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parameter AEMB_IWB = 32; ///< INST bus width
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parameter AEMB_IWB = 32; ///< INST bus width
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output dwb_wre_o; // From memif0 of aeMB2_memif.v
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output dwb_wre_o; // From memif0 of aeMB2_memif.v
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output [AEMB_IWB-1:2] iwb_adr_o; // From iwbif0 of aeMB2_iwbif.v
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output [AEMB_IWB-1:2] iwb_adr_o; // From iwbif0 of aeMB2_iwbif.v
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output iwb_cyc_o; // From iwbif0 of aeMB2_iwbif.v
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output iwb_cyc_o; // From iwbif0 of aeMB2_iwbif.v
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output [3:0] iwb_sel_o; // From iwbif0 of aeMB2_iwbif.v
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output [3:0] iwb_sel_o; // From iwbif0 of aeMB2_iwbif.v
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output iwb_stb_o; // From iwbif0 of aeMB2_iwbif.v
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output iwb_stb_o; // From iwbif0 of aeMB2_iwbif.v
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output iwb_tag_o; // From iwbif0 of aeMB2_iwbif.v
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output iwb_wre_o; // From iwbif0 of aeMB2_iwbif.v
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output iwb_wre_o; // From iwbif0 of aeMB2_iwbif.v
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output [AEMB_XWB-1:2] xwb_adr_o; // From memif0 of aeMB2_memif.v
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output [AEMB_XWB-1:2] xwb_adr_o; // From memif0 of aeMB2_memif.v
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output xwb_cyc_o; // From memif0 of aeMB2_memif.v
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output xwb_cyc_o; // From memif0 of aeMB2_memif.v
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output [31:0] xwb_dat_o; // From memif0 of aeMB2_memif.v
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output [31:0] xwb_dat_o; // From memif0 of aeMB2_memif.v
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output [3:0] xwb_sel_o; // From memif0 of aeMB2_memif.v
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output [3:0] xwb_sel_o; // From memif0 of aeMB2_memif.v
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.iwb_adr_o (iwb_adr_o[AEMB_IWB-1:2]),
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.iwb_adr_o (iwb_adr_o[AEMB_IWB-1:2]),
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.iwb_stb_o (iwb_stb_o),
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.iwb_stb_o (iwb_stb_o),
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.iwb_sel_o (iwb_sel_o[3:0]),
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.iwb_sel_o (iwb_sel_o[3:0]),
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.iwb_wre_o (iwb_wre_o),
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.iwb_wre_o (iwb_wre_o),
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.iwb_cyc_o (iwb_cyc_o),
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.iwb_cyc_o (iwb_cyc_o),
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.iwb_tag_o (iwb_tag_o),
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.ich_adr (ich_adr[AEMB_IWB-1:2]),
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.ich_adr (ich_adr[AEMB_IWB-1:2]),
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.fet_fb (fet_fb),
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.fet_fb (fet_fb),
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.rpc_if (rpc_if[31:2]),
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.rpc_if (rpc_if[31:2]),
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.rpc_mx (rpc_mx[31:2]),
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.rpc_mx (rpc_mx[31:2]),
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// Inputs
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// Inputs
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.iwb_ack_i (iwb_ack_i),
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.iwb_ack_i (iwb_ack_i),
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.iwb_dat_i (iwb_dat_i[31:0]),
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.iwb_dat_i (iwb_dat_i[31:0]),
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.ich_hit (ich_hit),
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.ich_hit (ich_hit),
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.msr_ex (msr_ex[7:5]),
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.hzd_bpc (hzd_bpc),
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.hzd_bpc (hzd_bpc),
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.hzd_fwd (hzd_fwd),
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.hzd_fwd (hzd_fwd),
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.bra_ex (bra_ex[1:0]),
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.bra_ex (bra_ex[1:0]),
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.bpc_ex (bpc_ex[31:2]),
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.bpc_ex (bpc_ex[31:2]),
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.gclk (gclk),
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.gclk (gclk),
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endmodule // aeMB2_edk62
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endmodule // aeMB2_edk62
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/*
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/*
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$Log: not supported by cvs2svn $
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$Log: not supported by cvs2svn $
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Revision 1.6 2008/04/26 17:57:43 sybreon
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Minor performance improvements.
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Revision 1.5 2008/04/26 01:11:30 sybreon
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Revision 1.5 2008/04/26 01:11:30 sybreon
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Fixed minor typos.
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Fixed minor typos.
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Revision 1.4 2008/04/26 01:09:05 sybreon
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Revision 1.4 2008/04/26 01:09:05 sybreon
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Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor.
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Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor.
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