| Line 32... |
Line 32... |
xwb_adr_o, iwb_wre_o, iwb_tag_o, iwb_stb_o, iwb_sel_o, iwb_cyc_o,
|
xwb_adr_o, iwb_wre_o, iwb_tag_o, iwb_stb_o, iwb_sel_o, iwb_cyc_o,
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iwb_adr_o, dwb_wre_o, dwb_tag_o, dwb_stb_o, dwb_sel_o, dwb_dat_o,
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iwb_adr_o, dwb_wre_o, dwb_tag_o, dwb_stb_o, dwb_sel_o, dwb_dat_o,
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dwb_cyc_o, dwb_adr_o,
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dwb_cyc_o, dwb_adr_o,
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// Inputs
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// Inputs
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xwb_dat_i, xwb_ack_i, sys_rst_i, sys_int_i, sys_ena_i, sys_clk_i,
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xwb_dat_i, xwb_ack_i, sys_rst_i, sys_int_i, sys_ena_i, sys_clk_i,
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iwb_dat_i, iwb_ack_i, exc_dwb, dwb_dat_i, dwb_ack_i
|
iwb_dat_i, iwb_ack_i, dwb_dat_i, dwb_ack_i
|
);
|
);
|
// BUS WIDTHS
|
// BUS WIDTHS
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parameter AEMB_IWB = 32; ///< INST bus width
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parameter AEMB_IWB = 32; ///< INST bus width
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parameter AEMB_DWB = 32; ///< DATA bus width
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parameter AEMB_DWB = 32; ///< DATA bus width
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parameter AEMB_XWB = 7; ///< XCEL bus width
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parameter AEMB_XWB = 7; ///< XCEL bus width
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| Line 80... |
Line 80... |
// End of automatics
|
// End of automatics
|
/*AUTOINPUT*/
|
/*AUTOINPUT*/
|
// Beginning of automatic inputs (from unused autoinst inputs)
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// Beginning of automatic inputs (from unused autoinst inputs)
|
input dwb_ack_i; // To memif0 of aeMB2_memif.v
|
input dwb_ack_i; // To memif0 of aeMB2_memif.v
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input [31:0] dwb_dat_i; // To memif0 of aeMB2_memif.v
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input [31:0] dwb_dat_i; // To memif0 of aeMB2_memif.v
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input [1:0] exc_dwb; // To pip0 of aeMB2_pipe.v
|
|
input iwb_ack_i; // To iche0 of aeMB2_iche.v, ...
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input iwb_ack_i; // To iche0 of aeMB2_iche.v, ...
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input [31:0] iwb_dat_i; // To iche0 of aeMB2_iche.v, ...
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input [31:0] iwb_dat_i; // To iche0 of aeMB2_iche.v, ...
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input sys_clk_i; // To pip0 of aeMB2_pipe.v
|
input sys_clk_i; // To pip0 of aeMB2_pipe.v
|
input sys_ena_i; // To pip0 of aeMB2_pipe.v
|
input sys_ena_i; // To pip0 of aeMB2_pipe.v
|
input sys_int_i; // To pip0 of aeMB2_pipe.v
|
input sys_int_i; // To pip0 of aeMB2_pipe.v
|
| Line 101... |
Line 100... |
wire [1:0] brk_if; // From pip0 of aeMB2_pipe.v
|
wire [1:0] brk_if; // From pip0 of aeMB2_pipe.v
|
wire [31:0] bsf_mx; // From exec0 of aeMB2_exec.v
|
wire [31:0] bsf_mx; // From exec0 of aeMB2_exec.v
|
wire dena; // From pip0 of aeMB2_pipe.v
|
wire dena; // From pip0 of aeMB2_pipe.v
|
wire dwb_fb; // From memif0 of aeMB2_memif.v
|
wire dwb_fb; // From memif0 of aeMB2_memif.v
|
wire [31:0] dwb_mx; // From memif0 of aeMB2_memif.v
|
wire [31:0] dwb_mx; // From memif0 of aeMB2_memif.v
|
|
wire [1:0] exc_dwb; // From memif0 of aeMB2_memif.v
|
wire exc_ill; // From exec0 of aeMB2_exec.v
|
wire exc_ill; // From exec0 of aeMB2_exec.v
|
wire exc_iwb; // From iwbif0 of aeMB2_iwbif.v
|
wire exc_iwb; // From iwbif0 of aeMB2_iwbif.v
|
wire fet_fb; // From iwbif0 of aeMB2_iwbif.v
|
wire fet_fb; // From iwbif0 of aeMB2_iwbif.v
|
wire gclk; // From pip0 of aeMB2_pipe.v
|
wire gclk; // From pip0 of aeMB2_pipe.v
|
wire gpha; // From pip0 of aeMB2_pipe.v
|
wire gpha; // From pip0 of aeMB2_pipe.v
|
| Line 324... |
Line 324... |
.dwb_mx (dwb_mx[31:0]),
|
.dwb_mx (dwb_mx[31:0]),
|
.dwb_sel_o (dwb_sel_o[3:0]),
|
.dwb_sel_o (dwb_sel_o[3:0]),
|
.dwb_stb_o (dwb_stb_o),
|
.dwb_stb_o (dwb_stb_o),
|
.dwb_tag_o (dwb_tag_o),
|
.dwb_tag_o (dwb_tag_o),
|
.dwb_wre_o (dwb_wre_o),
|
.dwb_wre_o (dwb_wre_o),
|
|
.exc_dwb (exc_dwb[1:0]),
|
.sel_mx (sel_mx[3:0]),
|
.sel_mx (sel_mx[3:0]),
|
.xwb_adr_o (xwb_adr_o[AEMB_XWB-1:2]),
|
.xwb_adr_o (xwb_adr_o[AEMB_XWB-1:2]),
|
.xwb_cyc_o (xwb_cyc_o),
|
.xwb_cyc_o (xwb_cyc_o),
|
.xwb_dat_o (xwb_dat_o[31:0]),
|
.xwb_dat_o (xwb_dat_o[31:0]),
|
.xwb_fb (xwb_fb),
|
.xwb_fb (xwb_fb),
|
