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https://opencores.org/ocsvn/aemb/aemb/trunk
[/] [aemb/] [trunk/] [rtl/] [verilog/] [aeMB2_exec.v] - Diff between revs 205 and 206
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| Rev 205 |
Rev 206 |
| Line 76... |
Line 76... |
reg exc_ill; // illegal instruction exception
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reg exc_ill; // illegal instruction exception
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//TODO: OPTIMISE!
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//TODO: OPTIMISE!
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wire wILL =
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wire wILL =
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((opc_of[5:4] == 2'o1) & opc_of[2]) | // illegal extended arithmetic
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((opc_of[5:4] == 2'o1) & opc_of[2]) | // illegal extended arithmetic
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((opc_of[5:4] == 2'o3) & &opc_of[1:0]); // illegal LD/ST
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(&opc_of[5:4] & &opc_of[1:0]); // illegal LD/ST
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//(opc_of == 6'o23) | (opc_of == 6'o24) | (opc_of == 6'o25) | (opc_of == 6'o26) | opc_of == 6'o27) |
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//(opc_of == 6'o23) | (opc_of == 6'o24) | (opc_of == 6'o25) | (opc_of == 6'o26) | opc_of == 6'o27) |
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//(opc_of == 6'o32) | (opc_of == 6'o34) | (opc_of == 6'o35) | (opc_of == 6'o36) | opc_of == 6'o37) |
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//(opc_of == 6'o32) | (opc_of == 6'o34) | (opc_of == 6'o35) | (opc_of == 6'o36) | opc_of == 6'o37) |
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//(opc_of == 6'o63) | (opc_of == 6'o67) | (opc_of == 6'o73) | (opc_of == 6'o77); // illegal load/store
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//(opc_of == 6'o63) | (opc_of == 6'o67) | (opc_of == 6'o73) | (opc_of == 6'o77); // illegal load/store
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always @(posedge gclk)
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always @(posedge gclk)
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