| Line 1... |
Line 1... |
/* $Id: aeMB2_gprf.v,v 1.3 2008-04-26 01:09:06 sybreon Exp $
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/* $Id: aeMB2_gprf.v,v 1.4 2008-04-26 17:57:43 sybreon Exp $
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**
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**
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** AEMB2 EDK 6.2 COMPATIBLE CORE
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** AEMB2 EDK 6.2 COMPATIBLE CORE
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** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
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** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
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**
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**
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** This file is part of AEMB.
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** This file is part of AEMB.
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| Line 92... |
Line 92... |
rd_mx <= #1 rd_ex;
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rd_mx <= #1 rd_ex;
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mux_mx <= #1 mux_ex;
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mux_mx <= #1 mux_ex;
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end
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end
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// LOAD SIZER
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// LOAD SIZER
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always @(/*AUTOSENSE*/dwb_mx or sel_mx) begin
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always @(/*AUTOSENSE*/dwb_mx or sel_mx or xwb_mx) begin
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case (sel_mx)
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case (sel_mx)
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// 8'bits
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// 8'bits
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4'h8: mem_mx <= #1 {24'd0, dwb_mx[31:24]};
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4'h8: mem_mx <= #1 {24'd0, dwb_mx[31:24]};
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4'h4: mem_mx <= #1 {24'd0, dwb_mx[23:16]};
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4'h4: mem_mx <= #1 {24'd0, dwb_mx[23:16]};
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4'h2: mem_mx <= #1 {24'd0, dwb_mx[15:8]};
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4'h2: mem_mx <= #1 {24'd0, dwb_mx[15:8]};
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| Line 104... |
Line 104... |
// 16'bits
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// 16'bits
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4'hC: mem_mx <= #1 {16'd0, dwb_mx[31:16]};
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4'hC: mem_mx <= #1 {16'd0, dwb_mx[31:16]};
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4'h3: mem_mx <= #1 {16'd0, dwb_mx[15:0]};
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4'h3: mem_mx <= #1 {16'd0, dwb_mx[15:0]};
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// 32'bits
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// 32'bits
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4'hF: mem_mx <= #1 dwb_mx;
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4'hF: mem_mx <= #1 dwb_mx;
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//4'h0: mem_mx <= #1 xwb_mx;
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// XSL bus
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4'h0: mem_mx <= #1 xwb_mx;
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default: mem_mx <= 32'hX;
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default: mem_mx <= 32'hX;
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endcase // case (sel_mx)
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endcase // case (sel_mx)
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end // always @ (...
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end // always @ (...
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// SELECT SOURCE
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// SELECT SOURCE
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localparam [2:0] MUX_ALU = 3'o7,
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localparam [2:0] MUX_SFR = 3'o7,
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MUX_SFR = 3'o5,
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MUX_BSF = 3'o6,
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MUX_BSF = 3'o4,
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MUX_MUL = 3'o5,
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MUX_MUL = 3'o3,
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MUX_MEM = 3'o4,
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MUX_MEM = 3'o2,
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MUX_RPC = 3'o1,
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MUX_RPC = 3'o2,
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MUX_ALU = 3'o1,
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MUX_NOP = 3'o0;
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MUX_NOP = 3'o0;
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always @(/*AUTOSENSE*/alu_mx or bsf_mx or mem_mx or mul_mx
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always @(/*AUTOSENSE*/alu_mx or bsf_mx or mem_mx or mul_mx
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or mux_mx or rpc_mx or sfr_mx)
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or mux_mx or rpc_mx or sfr_mx)
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case (mux_mx)
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case (mux_mx)
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| Line 129... |
Line 131... |
MUX_MUL: regd <= #1 mul_mx; // MULTIPLIER
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MUX_MUL: regd <= #1 mul_mx; // MULTIPLIER
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MUX_BSF: regd <= #1 bsf_mx; // SHIFTER
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MUX_BSF: regd <= #1 bsf_mx; // SHIFTER
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MUX_NOP: regd <= #1 32'h0;
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MUX_NOP: regd <= #1 32'h0;
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MUX_SFR: regd <= #1 sfr_mx;
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MUX_SFR: regd <= #1 sfr_mx;
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default: regd <= #1 32'hX;
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default: regd <= #1 32'hX;
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endcase // case (mux_rd)
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endcase // case (mux_mx)
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// REGISTER FILE - Infer LUT memory
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// REGISTER FILE - Infer LUT memory
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wire [5:0] wRD = {gpha, ich_dat[25:21]};
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wire [5:0] wRD0 = {gpha, ich_dat[25:21]};
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wire [5:0] wRA = {gpha, ich_dat[20:16]};
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wire [5:0] wRA0 = {gpha, ich_dat[20:16]};
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wire [5:0] wRB = {gpha, ich_dat[15:11]};
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wire [5:0] wRB0 = {gpha, ich_dat[15:11]};
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wire [5:0] wRW = {!gpha, rd_mx};
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wire [5:0] wRW0 = {!gpha, rd_mx};
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wire wWRE = grst | wrb_fb;
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assign opd_wr = rMEMD[wRW];
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assign opa_if = rMEMA[wRA];
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wire [31:0] wDA0,
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assign opb_if = rMEMB[wRB];
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wDB0,
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assign opd_if = rMEMD[wRD];
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wDD0;
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|
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always @(posedge gclk)
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assign opa_if = wDA0;
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if (grst | (dena & wrb_fb)) begin
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assign opb_if = wDB0;
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rMEMA[wRW] <= #1 regd;
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assign opd_if = wDD0;
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rMEMB[wRW] <= #1 regd;
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rMEMD[wRW] <= #1 regd;
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/* aeMB2_dparam AUTO_TEMPLATE "_\([a-z,0-9]+\)" (
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end
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.AW(6'd6),
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.DW(6'd32),
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// synopsys translate_off
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// initialise RAM to random contents for simulation only
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.clk_i(gclk),
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integer i;
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.ena_i(dena),
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initial begin
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for (i=0;i<64;i=i+1) begin
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.dat_i(regd),
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rMEMA[i] <= $random;
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.adr_i(wRW0[5:0]),
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rMEMB[i] <= $random;
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.wre_i(wWRE),
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rMEMD[i] <= $random;
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.dat_o(),
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end
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end
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.xwre_i(),
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// synopsys translate_on
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.xdat_i(),
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.xadr_i(wR@[5:0]),
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.xdat_o(wD@[31:0]),
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) */
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aeMB2_dparam
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#(/*AUTOINSTPARAM*/
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// Parameters
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.AW (6'd6), // Templated
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.DW (6'd32)) // Templated
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bank_A0
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(/*AUTOINST*/
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// Outputs
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.dat_o (), // Templated
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.xdat_o (wDA0[31:0]), // Templated
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// Inputs
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.adr_i (wRW0[5:0]), // Templated
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.dat_i (regd), // Templated
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.wre_i (wWRE), // Templated
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.xadr_i (wRA0[5:0]), // Templated
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.xdat_i (), // Templated
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.xwre_i (), // Templated
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.clk_i (gclk), // Templated
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.ena_i (dena)); // Templated
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aeMB2_dparam
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#(/*AUTOINSTPARAM*/
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// Parameters
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.AW (6'd6), // Templated
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.DW (6'd32)) // Templated
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bank_B0
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(/*AUTOINST*/
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// Outputs
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.dat_o (), // Templated
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.xdat_o (wDB0[31:0]), // Templated
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// Inputs
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.adr_i (wRW0[5:0]), // Templated
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.dat_i (regd), // Templated
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.wre_i (wWRE), // Templated
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.xadr_i (wRB0[5:0]), // Templated
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.xdat_i (), // Templated
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.xwre_i (), // Templated
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.clk_i (gclk), // Templated
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.ena_i (dena)); // Templated
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|
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aeMB2_dparam
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#(/*AUTOINSTPARAM*/
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// Parameters
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.AW (6'd6), // Templated
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.DW (6'd32)) // Templated
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bank_D0
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(/*AUTOINST*/
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// Outputs
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.dat_o (), // Templated
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.xdat_o (wDD0[31:0]), // Templated
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// Inputs
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.adr_i (wRW0[5:0]), // Templated
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.dat_i (regd), // Templated
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.wre_i (wWRE), // Templated
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.xadr_i (wRD0[5:0]), // Templated
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.xdat_i (), // Templated
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.xwre_i (), // Templated
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.clk_i (gclk), // Templated
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.ena_i (dena)); // Templated
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|
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endmodule // aeMB2_gprf
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endmodule // aeMB2_gprf
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|
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/*
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/*
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$Log: not supported by cvs2svn $
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$Log: not supported by cvs2svn $
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Revision 1.3 2008/04/26 01:09:06 sybreon
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Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor.
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|
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Revision 1.2 2008/04/20 16:34:32 sybreon
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Revision 1.2 2008/04/20 16:34:32 sybreon
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Basic version with some features left out.
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Basic version with some features left out.
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|
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Revision 1.1 2008/04/18 00:21:52 sybreon
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Revision 1.1 2008/04/18 00:21:52 sybreon
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Initial import.
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Initial import.
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*/
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*/
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No newline at end of file
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No newline at end of file
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`ifdef XXX
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wire [4:0] wRD0 = (gpha) ? ich_dat[25:21] : 5'd0;
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wire [4:0] wRA0 = (gpha) ? ich_dat[20:16] : 5'd0;
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wire [4:0] wRB0 = (gpha) ? ich_dat[15:11] : 5'd0;
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|
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wire [4:0] wRD1 = (!gpha) ? ich_dat[25:21] : 5'd0;
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wire [4:0] wRA1 = (!gpha) ? ich_dat[20:16] : 5'd0;
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wire [4:0] wRB1 = (!gpha) ? ich_dat[15:11] : 5'd0;
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|
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wire [4:0] wRW = rd_mx;
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|
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wire wWR0 = (!gpha & dena & wrb_fb) | grst;
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wire wWR1 = (gpha & dena & wrb_fb) | grst;
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wire wWA0 = wWR0;
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wire wWB0 = wWR0;
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wire wWD0 = wWR0;
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wire wWA1 = wWR1;
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wire wWB1 = wWR1;
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wire wWD1 = wWR1;
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|
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wire [31:0] wDA0,
|
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wDA1,
|
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wDB0,
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wDB1,
|
|
wDD0,
|
|
wDD1;
|
|
|
|
assign opa_if = wDA0 | wDA1;
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|
assign opb_if = wDB0 | wDB1;
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assign opd_if = wDD0 | wDD1;
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/* aeMB2_dparam AUTO_TEMPLATE "_\([a-z,0-9]+\)" (
|
|
.AW(6'd5),
|
|
.DW(6'd32),
|
|
|
|
.clk_i(gclk),
|
|
.ena_i(dena),
|
|
|
|
.dat_i(regd),
|
|
.adr_i(wRW[4:0]),
|
|
.wre_i(wW@),
|
|
.dat_o(),
|
|
|
|
.xwre_i(),
|
|
.xdat_i(),
|
|
.xadr_i(wR@[4:0]),
|
|
.xdat_o(wD@[31:0]),
|
|
) */
|
|
|
|
aeMB2_dparam
|
|
#(/*AUTOINSTPARAM*/
|
|
// Parameters
|
|
.AW (6'd5), // Templated
|
|
.DW (6'd32)) // Templated
|
|
bank_A0
|
|
(/*AUTOINST*/
|
|
// Outputs
|
|
.dat_o (), // Templated
|
|
.xdat_o (wDA0[31:0]), // Templated
|
|
// Inputs
|
|
.adr_i (wRW[4:0]), // Templated
|
|
.dat_i (regd), // Templated
|
|
.wre_i (wWA0), // Templated
|
|
.xadr_i (wRA0[4:0]), // Templated
|
|
.xdat_i (), // Templated
|
|
.xwre_i (), // Templated
|
|
.clk_i (gclk), // Templated
|
|
.ena_i (dena)); // Templated
|
|
|
|
aeMB2_dparam
|
|
#(/*AUTOINSTPARAM*/
|
|
// Parameters
|
|
.AW (6'd5), // Templated
|
|
.DW (6'd32)) // Templated
|
|
bank_B0
|
|
(/*AUTOINST*/
|
|
// Outputs
|
|
.dat_o (), // Templated
|
|
.xdat_o (wDB0[31:0]), // Templated
|
|
// Inputs
|
|
.adr_i (wRW[4:0]), // Templated
|
|
.dat_i (regd), // Templated
|
|
.wre_i (wWB0), // Templated
|
|
.xadr_i (wRB0[4:0]), // Templated
|
|
.xdat_i (), // Templated
|
|
.xwre_i (), // Templated
|
|
.clk_i (gclk), // Templated
|
|
.ena_i (dena)); // Templated
|
|
|
|
aeMB2_dparam
|
|
#(/*AUTOINSTPARAM*/
|
|
// Parameters
|
|
.AW (6'd5), // Templated
|
|
.DW (6'd32)) // Templated
|
|
bank_D0
|
|
(/*AUTOINST*/
|
|
// Outputs
|
|
.dat_o (), // Templated
|
|
.xdat_o (wDD0[31:0]), // Templated
|
|
// Inputs
|
|
.adr_i (wRW[4:0]), // Templated
|
|
.dat_i (regd), // Templated
|
|
.wre_i (wWD0), // Templated
|
|
.xadr_i (wRD0[4:0]), // Templated
|
|
.xdat_i (), // Templated
|
|
.xwre_i (), // Templated
|
|
.clk_i (gclk), // Templated
|
|
.ena_i (dena)); // Templated
|
|
|
|
aeMB2_dparam
|
|
#(/*AUTOINSTPARAM*/
|
|
// Parameters
|
|
.AW (6'd5), // Templated
|
|
.DW (6'd32)) // Templated
|
|
bank_A1
|
|
(/*AUTOINST*/
|
|
// Outputs
|
|
.dat_o (), // Templated
|
|
.xdat_o (wDA1[31:0]), // Templated
|
|
// Inputs
|
|
.adr_i (wRW[4:0]), // Templated
|
|
.dat_i (regd), // Templated
|
|
.wre_i (wWA1), // Templated
|
|
.xadr_i (wRA1[4:0]), // Templated
|
|
.xdat_i (), // Templated
|
|
.xwre_i (), // Templated
|
|
.clk_i (gclk), // Templated
|
|
.ena_i (dena)); // Templated
|
|
|
|
aeMB2_dparam
|
|
#(/*AUTOINSTPARAM*/
|
|
// Parameters
|
|
.AW (6'd5), // Templated
|
|
.DW (6'd32)) // Templated
|
|
bank_B1
|
|
(/*AUTOINST*/
|
|
// Outputs
|
|
.dat_o (), // Templated
|
|
.xdat_o (wDB1[31:0]), // Templated
|
|
// Inputs
|
|
.adr_i (wRW[4:0]), // Templated
|
|
.dat_i (regd), // Templated
|
|
.wre_i (wWB1), // Templated
|
|
.xadr_i (wRB1[4:0]), // Templated
|
|
.xdat_i (), // Templated
|
|
.xwre_i (), // Templated
|
|
.clk_i (gclk), // Templated
|
|
.ena_i (dena)); // Templated
|
|
|
|
aeMB2_dparam
|
|
#(/*AUTOINSTPARAM*/
|
|
// Parameters
|
|
.AW (6'd5), // Templated
|
|
.DW (6'd32)) // Templated
|
|
bank_D1
|
|
(/*AUTOINST*/
|
|
// Outputs
|
|
.dat_o (), // Templated
|
|
.xdat_o (wDD1[31:0]), // Templated
|
|
// Inputs
|
|
.adr_i (wRW[4:0]), // Templated
|
|
.dat_i (regd), // Templated
|
|
.wre_i (wWD1), // Templated
|
|
.xadr_i (wRD1[4:0]), // Templated
|
|
.xdat_i (), // Templated
|
|
.xwre_i (), // Templated
|
|
.clk_i (gclk), // Templated
|
|
.ena_i (dena)); // Templated
|
|
`endif
|
|
|
No newline at end of file
|
No newline at end of file
|
