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[/] [aemb/] [trunk/] [rtl/] [verilog/] [aeMB2_intu.v] - Diff between revs 131 and 134

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Line 1... Line 1... 
/* $Id: aeMB2_intu.v,v 1.4 2008-04-26 01:09:06 sybreon Exp $
 
/* $Id: aeMB2_intu.v,v 1.5 2008-04-26 17:57:43 sybreon Exp $
 
**
 
**
 
** AEMB2 EDK 6.2 COMPATIBLE CORE
 
** AEMB2 EDK 6.2 COMPATIBLE CORE
 
** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
 
** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
 
**
 
**
 
** This file is part of AEMB.
 
** This file is part of AEMB.
Line 77... Line 77... 
                        rMSR_ICE,
 
                        rMSR_ICE,
 
                        rMSR_BIP,
 
                        rMSR_BIP,
 
                        rMSR_IE,
 
                        rMSR_IE,
 
                        rMSR_BE;
 
                        rMSR_BE;
 
 
 
 
 
 
 
 
 
   // ADDER
 
   // ADDER
 
 
 
 
 
   /* Infer a ADD cell because ADD/SUB cannot be inferred cross
 
   /* Infer a ADD cell because ADD/SUB cannot be inferred cross
 
    technologies. */
 
    technologies. */
 
 
 
 
 
   // FIXME: Redesign this critical path
 
   // FIXME: Redesign this critical path
 
 
 
 
Line 152... Line 150... 
        mem_ex <= 30'h0;
 
        mem_ex <= 30'h0;
 
        // End of automatics
 
        // End of automatics
 
     end else if (dena) begin
 
     end else if (dena) begin
 
        alu_mx <= #1 alu_ex;
 
        alu_mx <= #1 alu_ex;
 
        alu_ex <= #1 (opc_of[5]) ? slm_ex : add_ex;
 
        alu_ex <= #1 (opc_of[5]) ? slm_ex : add_ex;
 
        mem_ex <= #1 add_ex[AEMB_DWB-1:2]; // LXX/SXX   
        mem_ex <= #1 wADD[AEMB_DWB-1:2]; // LXX/SXX     
        bpc_ex <= #1
 
        bpc_ex <= #1
 
                  (!opc_of[0] & ra_of[3]) ? // check for BRA
 
                  (!opc_of[0] & ra_of[3]) ? // check for BRA
 
                  opb_of[AEMB_IWB-1:2] : // BRA only
 
                  opb_of[AEMB_IWB-1:2] : // BRA only
 
                  add_ex[AEMB_IWB-1:2]; // RTD/BCC/BR
 
                  wADD[AEMB_IWB-1:2]; // RTD/BCC/BR
 
     end
 
     end
 
 
 
 
 
   // MSR SECTION
 
   // MSR SECTION
 
 
 
 
 
   /*
 
   /*
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   wire             fRTBD = (opc_of == 6'o55) & rd_of[1];
 
   wire             fRTBD = (opc_of == 6'o55) & rd_of[1];
 
 
 
 
 
   wire             fBRKI = (opc_of == 6'o56) & (ra_of[4:0] == 5'hD);
 
   wire             fBRKI = (opc_of == 6'o56) & (ra_of[4:0] == 5'hD);
 
   wire             fBRKB = ((opc_of == 6'o46) | (opc_of == 6'o56)) & (ra_of[4:0] == 5'hC);
 
   wire             fBRKB = ((opc_of == 6'o46) | (opc_of == 6'o56)) & (ra_of[4:0] == 5'hC);
 
 
 
 
 
   wire             fMOV = (opc_of == 6'o45);
 
   //wire           fMOV = (opc_of == 6'o45);
 
 
 
   wire             fMOV = opc_of[5] & !opc_of[4] & !opc_of[3] & opc_of[2] & !opc_of[1] & opc_of[0];
 
   wire             fMTS = fMOV & &imm_of[15:14];
 
   wire             fMTS = fMOV & &imm_of[15:14];
 
   wire             fMOP = fMOV & ~|imm_of[15:14];
 
   wire             fMOP = fMOV & ~|imm_of[15:14];
 
 
 
 
 
   reg [31:0]        sfr_ex;
 
   reg [31:0]        sfr_ex;
 
 
 
 
Line 242... Line 241... 
                   rMSR_BIP,
 
                   rMSR_BIP,
 
                   rMSR_CC,
 
                   rMSR_CC,
 
                   rMSR_IE,
 
                   rMSR_IE,
 
                   rMSR_BE
 
                   rMSR_BE
 
                   };
 
                   };
 
 
 
        /*
 
 
 
        rMSR_DCE <= #1
 
 
 
                   (fMTS) ? opa_of[7] :
 
 
 
                   (fMOP) ? wRES[7] :
 
 
 
                   rMSR_DCE;
 
 
 
 
 
 
 
        rMSR_ICE <= #1
 
 
 
                   (fMTS) ? opa_of[5] :
 
 
 
                   (fMOP) ? wRES[5] :
 
 
 
                   rMSR_ICE;
 
 
 
 
 
 
 
        rMSR_MTX <= #1
 
 
 
                   (fMTS) ? opa_of[4] :
 
 
 
                   (fMOP) ? wRES[4] :
 
 
 
                   rMSR_MTX;
 
 
 
 
 
 
 
        rMSR_BE <= #1
 
 
 
                   (fMTS) ? opa_of[0] :
 
 
 
                   (fMOP) ? wRES[0] :
 
 
 
                   rMSR_BE;
 
 
 
         */
 
 
 
 
 
        rMSR_DCE <= #1
 
        case ({fMTS, fMOP})
 
                   (fMTS) ? opa_of[7] :
 
          2'o2: {rMSR_DCE,
 
                   (fMOP) ? wRES[7] :
 
                 rMSR_ICE,
 
                   rMSR_DCE;
 
                 rMSR_MTX,
 
 
 
                 rMSR_BE} <= #1 {opa_of[7],
 
        rMSR_ICE <= #1
 
                                 opa_of[5],
 
                   (fMTS) ? opa_of[5] :
 
                                 opa_of[4],
 
                   (fMOP) ? wRES[5] :
 
                                 opa_of[0]};
 
                   rMSR_ICE;
 
          2'o1: {rMSR_DCE,
 
 
 
                 rMSR_ICE,
 
        rMSR_MTX <= #1
 
                 rMSR_MTX,
 
                   (fMTS) ? opa_of[4] :
 
                 rMSR_BE} <= #1 {wRES[7],
 
                   (fMOP) ? wRES[4] :
 
                                 wRES[5],
 
                   rMSR_MTX;
 
                                 wRES[4],
 
 
 
                                 wRES[0]};
 
        rMSR_BE <= #1
 
          default: {rMSR_DCE,
 
                   (fMTS) ? opa_of[0] :
 
                    rMSR_ICE,
 
                   (fMOP) ? wRES[0] :
 
                    rMSR_MTX,
 
                   rMSR_BE;
 
                    rMSR_BE} <= #1 {rMSR_DCE,
 
 
 
                                    rMSR_ICE,
 
 
 
                                    rMSR_MTX,
 
 
 
                                    rMSR_BE};
 
 
 
        endcase // case ({fMTS, fMOP})
 
 
 
 
 
        rMSR_IE <= #1
 
        case ({fMTS, fMOP})
 
                   (fBRKI) ? 1'b0 :
 
          2'o2: {rMSR_BIP,
 
                   (fRTID) ? 1'b1 :
 
                 rMSR_IE} <= #1 {opa_of[3],
 
                   (fMTS) ? opa_of[1] :
 
                                 opa_of[1]};
 
                   (fMOP) ? wRES[1] :
 
          2'o1: {rMSR_BIP,
 
                   rMSR_IE;
 
                 rMSR_IE} <= #1 {wRES[3],
 
 
 
                                 wRES[1]};
 
        rMSR_BIP <= #1
 
          default: begin
 
                    (fBRKB) ? 1'b1 :
 
             rMSR_BIP <= #1 (fBRKB | fRTBD) ? !rMSR_BIP : rMSR_BIP;
 
                    (fRTBD) ? 1'b0 :
 
             rMSR_IE <= #1 (fBRKI | fRTID) ? !rMSR_IE : rMSR_IE;
 
                    (fMTS) ? opa_of[3] :
 
          end
 
                    (fMOP) ? wRES[3] :
 
        endcase // case ({fMTS, fMOP})
 
                    rMSR_BIP;
 
 
 
 
 
 
 
 
 
        /*
 
 
 
        rMSR_IE <= #1
 
 
 
                   (fBRKI) ? 1'b0 :
 
 
 
                   (fRTID) ? 1'b1 :
 
 
 
                   (fMTS) ? opa_of[1] :
 
 
 
                   (fMOP) ? wRES[1] :
 
 
 
                   rMSR_IE;
 
 
 
 
 
 
 
        rMSR_BIP <= #1
 
 
 
                    (fBRKB) ? 1'b1 :
 
 
 
                    (fRTBD) ? 1'b0 :
 
 
 
                    (fMTS) ? opa_of[3] :
 
 
 
                    (fMOP) ? wRES[3] :
 
 
 
                    rMSR_BIP;
 
 
 
        */
 
     end // if (dena)
 
     end // if (dena)
 
 
 
 
 
   // BARREL C
 
   // BARREL C
 
   wire fADDSUB = (opc_of[5:2] == 4'h0) | (opc_of[5:2] == 4'h2);
 
   wire fADDSUB = (opc_of[5:2] == 4'h0) | (opc_of[5:2] == 4'h2);
 
   wire fSHIFT  = (opc_of == 6'o44) & (imm_of[6:5] != 2'o3);
 
   wire fSHIFT  = (opc_of == 6'o44) & (imm_of[6:5] != 2'o3);
Line 310... Line 348... 
 
 
 
 
endmodule // aeMB2_intu
 
endmodule // aeMB2_intu
 
 
 
 
 
/*
 
/*
 
 $Log: not supported by cvs2svn $
 
 $Log: not supported by cvs2svn $
 
 
 
 Revision 1.4  2008/04/26 01:09:06  sybreon
 
 
 
 Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor.
 
 
 
 
 
 Revision 1.3  2008/04/23 14:18:30  sybreon
 
 Revision 1.3  2008/04/23 14:18:30  sybreon
 
 Fixed CMP bug.
 
 Fixed CMP bug.
 
 
 
 
 
 Revision 1.2  2008/04/21 12:11:38  sybreon
 
 Revision 1.2  2008/04/21 12:11:38  sybreon
 
 Passes arithmetic tests with single thread.
 
 Passes arithmetic tests with single thread.

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