| Line 1... |
Line 1... |
/* $Id: aeMB2_intu.v,v 1.6 2008-04-28 08:15:25 sybreon Exp $
|
/* $Id: aeMB2_intu.v,v 1.7 2008-05-01 12:00:18 sybreon Exp $
|
**
|
**
|
** AEMB2 EDK 6.2 COMPATIBLE CORE
|
** AEMB2 EDK 6.2 COMPATIBLE CORE
|
** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
|
** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
|
**
|
**
|
** This file is part of AEMB.
|
** This file is part of AEMB.
|
| Line 97... |
Line 97... |
wire [31:0] wADD;
|
wire [31:0] wADD;
|
wire wADC;
|
wire wADC;
|
|
|
wire fCCC = !opc_of[5] & opc_of[1]; // & !opc_of[4]
|
wire fCCC = !opc_of[5] & opc_of[1]; // & !opc_of[4]
|
wire fSUB = !opc_of[5] & opc_of[0]; // & !opc_of[4]
|
wire fSUB = !opc_of[5] & opc_of[0]; // & !opc_of[4]
|
wire fCMP = !opc_of[3] & imm_of[1]; // & imm_of[0]; // unsigned
|
wire fCMP = !opc_of[3] & imm_of[1]; // unsigned only
|
wire wCMP = (fCMP) ? (opa_of > opb_of) : wADD[31];
|
wire wCMP = (fCMP) ? !wADC : wADD[31]; // cmpu adjust
|
|
|
wire [31:0] wOPA = (fSUB) ? ~opa_of : opa_of;
|
wire [31:0] wOPA = (fSUB) ? ~opa_of : opa_of;
|
wire wOPC = (fCCC) ? rMSR_CC : fSUB;
|
wire wOPC = (fCCC) ? rMSR_CC : fSUB;
|
|
|
assign {wADC, wADD} = (opb_of + wOPA) + wOPC; // add carry
|
assign {wADC, wADD} = (opb_of + wOPA) + wOPC; // add carry
|
|
|
always @(/*AUTOSENSE*/wADC or wADD or wCMP) begin
|
always @(/*AUTOSENSE*/wADC or wADD or wCMP) begin
|
{add_c, add_ex} <= #1 {wADC, wCMP, wADD[30:0]}; // add with carry
|
{add_c, add_ex} <= #1 {wADC, wCMP, wADD[30:0]}; // add with carry
|
//(!opc_of[3] & imm_of[0]) ?
|
|
//{wADC, wCMP , wADD[30:0]} : // add with carry
|
|
//{wADC, wADD[31:0]} ; // add with carry
|
|
end
|
end
|
|
|
// SHIFT/LOGIC/MOVE
|
// SHIFT/LOGIC/MOVE
|
reg [31:0] slm_ex;
|
reg [31:0] slm_ex;
|
|
|
| Line 208... |
Line 205... |
|
|
wire fBRKI = (opc_of == 6'o56) & (ra_of[4:0] == 5'hD);
|
wire fBRKI = (opc_of == 6'o56) & (ra_of[4:0] == 5'hD);
|
wire fBRKB = ((opc_of == 6'o46) | (opc_of == 6'o56)) & (ra_of[4:0] == 5'hC);
|
wire fBRKB = ((opc_of == 6'o46) | (opc_of == 6'o56)) & (ra_of[4:0] == 5'hC);
|
|
|
wire fMOV = (opc_of == 6'o45);
|
wire fMOV = (opc_of == 6'o45);
|
//wire fMOV = opc_of[5] & !opc_of[4] & !opc_of[3] & opc_of[2] & !opc_of[1] & opc_of[0];
|
|
//wire fMOV = ({!opc_of[5], opc_of[4:3], !opc_of[2], opc_of[1], !opc_of[0]} == 6'd0);
|
|
wire fMTS = fMOV & &imm_of[15:14];
|
wire fMTS = fMOV & &imm_of[15:14];
|
wire fMOP = fMOV & ~|imm_of[15:14];
|
wire fMOP = fMOV & ~|imm_of[15:14];
|
|
|
reg [31:0] sfr_ex;
|
reg [31:0] sfr_ex;
|
|
|
| Line 244... |
Line 239... |
rMSR_BIP,
|
rMSR_BIP,
|
rMSR_CC,
|
rMSR_CC,
|
rMSR_IE,
|
rMSR_IE,
|
rMSR_BE
|
rMSR_BE
|
};
|
};
|
/*
|
|
rMSR_DTE <= #1
|
|
(fMTS) ? opa_of[7] :
|
|
(fMOP) ? wRES[7] :
|
|
rMSR_DTE;
|
|
|
|
rMSR_ITE <= #1
|
|
(fMTS) ? opa_of[5] :
|
|
(fMOP) ? wRES[5] :
|
|
rMSR_ITE;
|
|
|
|
rMSR_MTX <= #1
|
|
(fMTS) ? opa_of[4] :
|
|
(fMOP) ? wRES[4] :
|
|
rMSR_MTX;
|
|
|
|
rMSR_BE <= #1
|
|
(fMTS) ? opa_of[0] :
|
|
(fMOP) ? wRES[0] :
|
|
rMSR_BE;
|
|
*/
|
|
|
|
case ({fMTS, fMOP})
|
rMSR_DTE <= #1
|
2'o2: {rMSR_DTE,
|
(fMTS) ? opa_of[7] :
|
rMSR_ITE,
|
(fMOP) ? wRES[7] :
|
rMSR_MTX,
|
rMSR_DTE;
|
rMSR_BE} <= #1 {opa_of[7],
|
|
opa_of[5],
|
rMSR_ITE <= #1
|
opa_of[4],
|
(fMTS) ? opa_of[5] :
|
opa_of[0]};
|
(fMOP) ? wRES[5] :
|
2'o1: {rMSR_DTE,
|
rMSR_ITE;
|
rMSR_ITE,
|
|
rMSR_MTX,
|
rMSR_MTX <= #1
|
rMSR_BE} <= #1 {wRES[7],
|
(fMTS) ? opa_of[4] :
|
wRES[5],
|
(fMOP) ? wRES[4] :
|
wRES[4],
|
rMSR_MTX;
|
wRES[0]};
|
|
default: {rMSR_DTE,
|
rMSR_BE <= #1
|
rMSR_ITE,
|
(fMTS) ? opa_of[0] :
|
rMSR_MTX,
|
(fMOP) ? wRES[0] :
|
rMSR_BE} <= #1 {rMSR_DTE,
|
rMSR_BE;
|
rMSR_ITE,
|
|
rMSR_MTX,
|
|
rMSR_BE};
|
|
endcase // case ({fMTS, fMOP})
|
|
|
|
case ({fMTS, fMOP})
|
|
2'o2: {rMSR_BIP,
|
|
rMSR_IE} <= #1 {opa_of[3],
|
|
opa_of[1]};
|
|
2'o1: {rMSR_BIP,
|
|
rMSR_IE} <= #1 {wRES[3],
|
|
wRES[1]};
|
|
default: begin
|
|
rMSR_BIP <= #1 (fBRKB | fRTBD) ? !rMSR_BIP : rMSR_BIP;
|
|
rMSR_IE <= #1 (fBRKI | fRTID) ? !rMSR_IE : rMSR_IE;
|
|
end
|
|
endcase // case ({fMTS, fMOP})
|
|
|
|
|
rMSR_IE <= #1
|
|
(fBRKI) ? 1'b0 :
|
|
(fRTID) ? 1'b1 :
|
|
(fMTS) ? opa_of[1] :
|
|
(fMOP) ? wRES[1] :
|
|
rMSR_IE;
|
|
|
|
rMSR_BIP <= #1
|
|
(fBRKB) ? 1'b1 :
|
|
(fRTBD) ? 1'b0 :
|
|
(fMTS) ? opa_of[3] :
|
|
(fMOP) ? wRES[3] :
|
|
rMSR_BIP;
|
/*
|
/*
|
rMSR_IE <= #1
|
|
(fBRKI) ? 1'b0 :
|
case ({fMTS, fMOP})
|
(fRTID) ? 1'b1 :
|
2'o2: {rMSR_DTE,
|
(fMTS) ? opa_of[1] :
|
rMSR_ITE,
|
(fMOP) ? wRES[1] :
|
rMSR_MTX,
|
rMSR_IE;
|
rMSR_BE} <= #1 {opa_of[7],
|
|
opa_of[5],
|
rMSR_BIP <= #1
|
opa_of[4],
|
(fBRKB) ? 1'b1 :
|
opa_of[0]};
|
(fRTBD) ? 1'b0 :
|
2'o1: {rMSR_DTE,
|
(fMTS) ? opa_of[3] :
|
rMSR_ITE,
|
(fMOP) ? wRES[3] :
|
rMSR_MTX,
|
rMSR_BIP;
|
rMSR_BE} <= #1 {wRES[7],
|
|
wRES[5],
|
|
wRES[4],
|
|
wRES[0]};
|
|
default: {rMSR_DTE,
|
|
rMSR_ITE,
|
|
rMSR_MTX,
|
|
rMSR_BE} <= #1 {rMSR_DTE,
|
|
rMSR_ITE,
|
|
rMSR_MTX,
|
|
rMSR_BE};
|
|
endcase // case ({fMTS, fMOP})
|
|
|
|
case ({fMTS, fMOP})
|
|
2'o2: {rMSR_BIP,
|
|
rMSR_IE} <= #1 {opa_of[3],
|
|
opa_of[1]};
|
|
2'o1: {rMSR_BIP,
|
|
rMSR_IE} <= #1 {wRES[3],
|
|
wRES[1]};
|
|
default: begin
|
|
rMSR_BIP <= #1 (fBRKB | fRTBD) ? !rMSR_BIP : rMSR_BIP;
|
|
rMSR_IE <= #1 (fBRKI | fRTID) ? !rMSR_IE : rMSR_IE;
|
|
end
|
|
endcase // case ({fMTS, fMOP})
|
*/
|
*/
|
end // if (dena)
|
end // if (dena)
|
|
|
// BARREL C
|
// BARREL C
|
wire fADDSUB = (opc_of[5:2] == 4'h0) | (opc_of[5:2] == 4'h2);
|
wire fADDSUB = !opc_of[5] & !opc_of[4] & !opc_of[2];
|
wire fSHIFT = (opc_of == 6'o44) & (imm_of[6:5] != 2'o3);
|
// (opc_of[5:2] == 4'h0) | (opc_of[5:2] == 4'h2);
|
|
wire fSHIFT = (opc_of == 6'o44) & &imm_of[6:5];
|
|
|
always @(posedge gclk)
|
always @(posedge gclk)
|
if (grst) begin
|
if (grst) begin
|
/*AUTORESET*/
|
/*AUTORESET*/
|
end else if (dena) begin
|
end else if (dena) begin
|
| Line 339... |
Line 334... |
rMSR_C <= 1'h0;
|
rMSR_C <= 1'h0;
|
rMSR_CC <= 1'h0;
|
rMSR_CC <= 1'h0;
|
// End of automatics
|
// End of automatics
|
end else if (dena) begin
|
end else if (dena) begin
|
rMSR_CC <= #1 rMSR_C;
|
rMSR_CC <= #1 rMSR_C;
|
|
|
rMSR_C <= #1
|
rMSR_C <= #1
|
(fMTS) ? opa_of[2] :
|
(fMTS) ? opa_of[2] :
|
(fMOP) ? wRES[2] :
|
(fMOP) ? wRES[2] :
|
(fSHIFT) ? opa_of[0] : // SRA/SRL/SRC
|
(fSHIFT) ? opa_of[0] : // SRA/SRL/SRC
|
(fADDSUB) ? add_c : // ADD/SUB/ADDC/SUBC
|
(fADDSUB) ? add_c : // ADD/SUB/ADDC/SUBC
|
rMSR_CC;
|
rMSR_CC;
|
|
|
|
/*
|
|
case ({fMTS,fMOP,fSHIFT,fADDSUB})
|
|
4'h8: rMSR_C <= #1 opa_of[2];
|
|
4'h4: rMSR_C <= #1 wRES[2];
|
|
4'h2: rMSR_C <= #1 opa_of[0];
|
|
4'h1: rMSR_C <= #1 add_c;
|
|
default: rMSR_C <= #1 rMSR_CC;
|
|
endcase // case ({fMTS,fMOP,fSHIFT,fADDSUB})
|
|
*/
|
end
|
end
|
|
|
endmodule // aeMB2_intu
|
endmodule // aeMB2_intu
|
|
|
/*
|
/*
|
$Log: not supported by cvs2svn $
|
$Log: not supported by cvs2svn $
|
|
Revision 1.6 2008/04/28 08:15:25 sybreon
|
|
Optimisations.
|
|
|
Revision 1.5 2008/04/26 17:57:43 sybreon
|
Revision 1.5 2008/04/26 17:57:43 sybreon
|
Minor performance improvements.
|
Minor performance improvements.
|
|
|
Revision 1.4 2008/04/26 01:09:06 sybreon
|
Revision 1.4 2008/04/26 01:09:06 sybreon
|
Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor.
|
Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor.
|
