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/* $Id: aeMB2_sim.v,v 1.1 2007-12-18 18:54:36 sybreon Exp $
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/* $Id: aeMB2_sim.v,v 1.2 2007-12-29 00:31:48 sybreon Exp $
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**
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**
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** AEMB2 SIMULATION WRAPPER
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** AEMB2 SIMULATION WRAPPER
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**
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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**
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**
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** This file is part of AEMB.
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** This file is part of AEMB.
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**
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**
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** AEMB is free software: you can redistribute it and/or modify it
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** AEMB is free software: you can redistribute it and/or modify it
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parameter FSL = 1; ///< enable FSL bus
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parameter FSL = 1; ///< enable FSL bus
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parameter DIV = 0; ///< enable hardware divider
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parameter DIV = 0; ///< enable hardware divider
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/*AUTOOUTPUT*/
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/*AUTOOUTPUT*/
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// Beginning of automatic outputs (from unused autoinst outputs)
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// Beginning of automatic outputs (from unused autoinst outputs)
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output [6:2] cwb_adr_o; // From cpu of aeMB2_edk32.v
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output [6:2] cwb_adr_o; // From sim of aeMB2_edk32.v
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output [31:0] cwb_dat_o; // From cpu of aeMB2_edk32.v
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output [31:0] cwb_dat_o; // From sim of aeMB2_edk32.v
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output [3:0] cwb_sel_o; // From cpu of aeMB2_edk32.v
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output [3:0] cwb_sel_o; // From sim of aeMB2_edk32.v
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output cwb_stb_o; // From cpu of aeMB2_edk32.v
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output cwb_stb_o; // From sim of aeMB2_edk32.v
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output [1:0] cwb_tga_o; // From cpu of aeMB2_edk32.v
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output [1:0] cwb_tga_o; // From sim of aeMB2_edk32.v
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output cwb_wre_o; // From cpu of aeMB2_edk32.v
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output cwb_wre_o; // From sim of aeMB2_edk32.v
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output [DWB-1:2] dwb_adr_o; // From cpu of aeMB2_edk32.v
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output [DWB-1:2] dwb_adr_o; // From sim of aeMB2_edk32.v
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output dwb_cyc_o; // From cpu of aeMB2_edk32.v
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output dwb_cyc_o; // From sim of aeMB2_edk32.v
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output [31:0] dwb_dat_o; // From cpu of aeMB2_edk32.v
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output [31:0] dwb_dat_o; // From sim of aeMB2_edk32.v
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output [3:0] dwb_sel_o; // From cpu of aeMB2_edk32.v
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output [3:0] dwb_sel_o; // From sim of aeMB2_edk32.v
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output dwb_stb_o; // From cpu of aeMB2_edk32.v
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output dwb_stb_o; // From sim of aeMB2_edk32.v
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output dwb_tga_o; // From cpu of aeMB2_edk32.v
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output dwb_tga_o; // From sim of aeMB2_edk32.v
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output dwb_wre_o; // From cpu of aeMB2_edk32.v
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output dwb_wre_o; // From sim of aeMB2_edk32.v
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output [IWB-1:2] iwb_adr_o; // From cpu of aeMB2_edk32.v
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output [IWB-1:2] iwb_adr_o; // From sim of aeMB2_edk32.v
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output iwb_stb_o; // From cpu of aeMB2_edk32.v
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output iwb_stb_o; // From sim of aeMB2_edk32.v
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output iwb_tga_o; // From cpu of aeMB2_edk32.v
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output iwb_tga_o; // From sim of aeMB2_edk32.v
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output iwb_wre_o; // From cpu of aeMB2_edk32.v
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output iwb_wre_o; // From sim of aeMB2_edk32.v
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// End of automatics
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// End of automatics
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/*AUTOINPUT*/
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/*AUTOINPUT*/
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// Beginning of automatic inputs (from unused autoinst inputs)
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// Beginning of automatic inputs (from unused autoinst inputs)
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input cwb_ack_i; // To cpu of aeMB2_edk32.v
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input cwb_ack_i; // To sim of aeMB2_edk32.v
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input [31:0] cwb_dat_i; // To cpu of aeMB2_edk32.v
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input [31:0] cwb_dat_i; // To sim of aeMB2_edk32.v
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input dwb_ack_i; // To cpu of aeMB2_edk32.v
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input dwb_ack_i; // To sim of aeMB2_edk32.v
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input [31:0] dwb_dat_i; // To cpu of aeMB2_edk32.v
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input [31:0] dwb_dat_i; // To sim of aeMB2_edk32.v
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input iwb_ack_i; // To cpu of aeMB2_edk32.v
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input iwb_ack_i; // To sim of aeMB2_edk32.v
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input [31:0] iwb_dat_i; // To cpu of aeMB2_edk32.v
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input [31:0] iwb_dat_i; // To sim of aeMB2_edk32.v
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input sys_clk_i; // To cpu of aeMB2_edk32.v
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input sys_clk_i; // To sim of aeMB2_edk32.v
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input sys_int_i; // To cpu of aeMB2_edk32.v
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input sys_int_i; // To sim of aeMB2_edk32.v
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input sys_rst_i; // To cpu of aeMB2_edk32.v
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input sys_rst_i; // To sim of aeMB2_edk32.v
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// End of automatics
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// End of automatics
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/*AUTOWIRE*/
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/*AUTOWIRE*/
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aeMB2_edk32
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aeMB2_edk32
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#(/*AUTOINSTPARAM*/
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#(/*AUTOINSTPARAM*/
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*/
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*/
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end // if (sim.ena_i)
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end // if (sim.ena_i)
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// synopsys translate_on
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// synopsys translate_on
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endmodule // aeMB2_sim
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endmodule // aeMB2_sim
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/* $Log: not supported by cvs2svn $ */
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/* $Log: not supported by cvs2svn $
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/* Revision 1.1 2007/12/18 18:54:36 sybreon
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/* Partitioned simulation model.
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/* */
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